Patents by Inventor Phillipe Dupuis

Phillipe Dupuis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Field effect transistor having differing power dissipation across an array of transistors
    Patent number: 6603157
    Abstract: A field effect transistor (30) has an array of transistors (31) made up of bonding pads (45-47) and sub-arrays of transistors (41-43). The bonding pads (45-47) are distributed between the sub-arrays of transistors (41-43) to reduce the maximum temperature that any portion of the FET (30) is exposed to while the FET (30) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion (101) of an array of transistors (95).
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: August 5, 2003
    Assignee: Motorola, Inc.
    Inventors: Phillipe Dupuy, Steven L. Merchant, Robert W. Baird
  • Field effect transistor and method of making
    Patent number: 6423991
    Abstract: A field effect transistor (30) has an array of transistors (31) made up of bonding pads (45-47) and sub-arrays of transistors (41-43). The bonding pads (45-47) are distributed between the sub-arrays of transistors (41-43) to reduce the maximum temperature that any portion of the FET (30) is exposed to while the FET (30) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion (101) of an array of transistors (95).
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: July 23, 2002
    Assignee: Motorola, Inc.
    Inventors: Phillipe Dupuy, Steven L. Merchant, Robert W. Baird
  • Field effect transistor and method of making
    Publication number: 20020036329
    Abstract: A field effect transistor (30) has an array of transistors (31) made up of bonding pads (45-47) and sub-arrays of transistors (41-43). The bonding pads (45-47) are distributed between the sub-arrays of transistors (41-43) to reduce the maximum temperature that any portion of the FET (30) is exposed to while the FET (30) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion (101) of an array of transistors (95).
    Type: Application
    Filed: November 2, 2001
    Publication date: March 28, 2002
    Inventors: Phillipe Dupuy, Steven L. Merchant, Robert W. Baird
  • Method of changing the power dissipation across an array of transistors
    Patent number: 6140184
    Abstract: A field effect transistor (30) has an array of transistors (31) made up of bonding pads (45-47) and sub-arrays of transistors (41-43). The bonding pads (45-47) are distributed between the sub-arrays of transistors (41-43) to reduce the maximum temperature that any portion of the FET (30) is exposed to while the FET (30) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion (101) of an array of transistors (95).
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: October 31, 2000
    Assignee: Motorola, Inc.
    Inventors: Phillipe Dupuy, Steven L. Merchant, Robert W. Baird
  • Microwave plate antenna in particular for Doppler radar
    Patent number: 4899163
    Abstract: The antenna constituted by a plurality of identical parallel and symmetrical linear sub-networks (a7, a6, . . . a1, a'1, a'2, . . . , a'7). The centres of symmetry (b7, b.notident.b, . . . , b1, b'1, b'2 . . . , b'7) of the sub-networks (a7 to a'7) are aligned on a line (c) perpendicular to their diameter and are fed in phase. Each sub-network is constituted by a plurality of radiating elements in even numbers disposed at regular intervals and which radiate from fields displaced from 180.degree. from one radiating element to the following. The pitch of the sub-network is approximately equal to a wave-length guided on the substrate of the printed circuit. Each radiating element is a conducting square surface the side of which is approximately equal to half the guided wavelength with one corner connected galvanically to the feed line. The direction of the surfaces change from one element to the following element.
    Type: Grant
    Filed: August 9, 1988
    Date of Patent: February 6, 1990
    Assignee: Le Centre Regional D'Innovation et de Transfert de Technologie de Bretagne Loi Le Centre National de la Recherche Scientifique, Etablissement Public National a Caractere Scientifique et Technologiqu
    Inventors: Jean-Pierre L. M. Daniel, Phillipe Dupuis, Jean-Luc Alanic