Patents by Inventor Phillipe Luc

Phillipe Luc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data transfer between a master and slave
    Patent number: 9378175
    Abstract: A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configure
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: June 28, 2016
    Assignee: ARM Limited
    Inventors: Nicolas Chaussade, Pierre Michel Broyer, Phillipe Luc
  • Data transfer between a master and slave
    Publication number: 20080147921
    Abstract: A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configure
    Type: Application
    Filed: November 1, 2007
    Publication date: June 19, 2008
    Applicant: ARM Limited
    Inventors: Nicolas Chaussade, Pierre Michel Broyer, Phillipe Luc