Patents by Inventor Phillippe Roche

Phillippe Roche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device
    Patent number: 8837206
    Abstract: A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: September 16, 2014
    Assignee: STMicroelectronics (Crolles 2)
    Inventors: Maximilien Glorieux, Sylvain Clerc, Gilles Gasiot, Phillippe Roche
  • Content addressable memory circuit with improved memory cell stability
    Patent number: 7233512
    Abstract: A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common terminal (VPL) exists for the memory cells. Capacitors are added between the internal nodes of each of the memory cells and common terminal for memory cell stability.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: June 19, 2007
    Assignees: STMicroelectronics, Inc., STMicroelectronics SA
    Inventors: Mark Lysinger, Francois Jacquet, Phillippe Roche
  • Content addressable memory circuit with improved memory cell stability
    Publication number: 20060171183
    Abstract: A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common terminal (VPL) exists for the memory cells. Capacitors are added between the internal nodes of each of the memory cells and common terminal for memory cell stability.
    Type: Application
    Filed: February 1, 2005
    Publication date: August 3, 2006
    Applicant: STMicroelectronics, Inc.
    Inventors: Mark Lysinger, Francois Jacquet, Phillippe Roche