Abstract: Properties of a solid state drive can be shown in a visual representation, which includes aspects of the solid state drive, such as remaining lifetime, read and write workload, life acceleration characteristics, and temperature correlation of data and errors.

Abstract: Data, such as indicators of storage devices, are logged periodically with the recorded time. The time logged data, e.g., data collected at different times, can be used to calculate properties and characteristics of the storage devices, including instantaneous properties and time evolution properties.

Abstract: An embodiment is a technique to adapt behavior of a solid-state drive (SSD) to extend lifespan of the SSD. Real environmental information is received from an environmental processor. The real environmental information corresponds to an environment of the SSD. A behavior model is selected based on a real environmental model and an internal data usage model. If a new behavior model is selected, the environmental processor is informed about the new behavior model. The environmental processor sends control commands to a power management module to apply new power policy to the SSD. Information on the new behavior model is made available for query. If current behavior model is selected, the current behavior model is maintained.

Abstract: An embodiment is a technique to estimate lifespan of a solid-state drive (SSD). Real environmental information from an environmental processor is received. The real environmental information corresponds to an environment of a solid-state drive (SSD). The lifespan of the SSD is estimated using the real environmental information and an internal data usage model. The estimated lifespan is made available for retrieval.

Abstract: An embodiment is a technique to adapt behavior of a solid-state drive (SSD) to extend lifespan of the SSD. Real environmental information is received from an environmental processor. The real environmental information corresponds to an environment of the SSD. A behavior model is selected based on a real environmental model and an internal data usage model. If a new behavior model is selected, the environmental processor is informed about the new behavior model. The environmental processor sends control commands to a power management module to apply new power policy to the SSD. Information on the new behavior model is made available for query. If current behavior model is selected, the current behavior model is maintained.

Abstract: An embodiment is a technique to generate failure mode information for solid-state drive (SSD) in real environment. An environmental acquisition module acquires environmental information from an environmental sensor. A learning and update module generates an environmental profile based on the acquired environmental information. A failure acquisition module associates failure information from an SSD controller that controls an SSD with the environmental profile. An operation analyzer analyzes the associated failure information using pre-determined information provided by a database to generate failure mode information. A decision module decides if the failure mode information is valid.

Abstract: A high performance register that can be used as a pipelined register in logic chips that are designed using a pulsed logic methodology is described. The register features minimal setup time, pulse catching and pulse launching. The register circuitry complies with and implements a circuit-level test methodology for pulsed logic that features the ability to inhibit the reset of pulses, to force resets and to operate the circuits in a pseudo static mode. The register also complies with the level sensitive scan design (LSSD) methodology. Also described is a state-holding static master-slave register that complies with a pulsed logic design methodology, the register exhibiting an automatic power reduction feature and a simplified modular register bit design which can easily be adapted to either static domino or pulsed logic. The register is also LSSD compliant. Also described is the means and method for allowing static transmission gate input registers to comply with the static evaluate test mode.