Abstract: A method for determining an optimal design for wiring interconnect and driver power for a designed target delay begins at the floor planning stages of the chip design and may be repeated during the design process. The designer initially specifies a maximum width that wires are allowed to use and a target delay value. Then the designer gives values to weights used in the calculation of an optimization function G(d,p,w), where d is the delay, p is the power, and w is wire width. An "ideal" slope ##EQU1## is calculated, assuming zero resistance. The designer chooses a slope decrease value from the "ideal" slope value. For each set wire width, the delay (at the proper slope) belonging to that particular wire width is obtained. With these inputs, an optimization program according to the invention is run. This program then calculates values of the function G(d,p,w) for increasing wire pitches, starting with the minimum allowed by the technology.