Patents by Inventor Phung Nguyen

Phung Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230368119
    Abstract: This disclosure relates to systems and methods of using machine vision in a distribution network environment. In particular, this disclosure relates to systems and methods for automatically monitoring zones within a distribution facility with machine vision and generating notifications.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 16, 2023
    Inventors: David C. Lin, Shahpour Ashaari, Assebe Eshete, Mario Andre Salisbury, Phung Nguyen, Erich Joseph Petre
  • Patent number: 8987778
    Abstract: Embodiments of the invention provide increased ESD protection suitable for high-voltage devices. In one embodiment, an internal DMOS circuit is placed in parallel with a lateral NPN ESD clamp. The clamp has both a high holding voltage, above the operating voltage of the DMOS circuit, and a high maximum current before breakdown. The discharge path of the clamp includes a high-voltage lightly doped well containing a low-voltage higher doped well. The dopant of both wells is the same type, and the interface between the two defines a graded junction. The emitter of the entire circuit is grounded and the collector is coupled to the voltage of the DMOS circuit.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: March 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Yue Zu, Hoang Phung Nguyen, Thomas E. Harrington, III
  • Publication number: 20070069309
    Abstract: A substrate having a buried well is provided. The substrate may be formed by implanting ions in a surface well of a first substrate and subsequently forming a semiconductor layer, such as an epitaxial layer, over the surface well. In this manner, the surface well becomes a buried well having a semiconductor layer that is substantially undoped formed thereon. In an embodiment, a transistor is formed on the substrate. Because the epitaxial layer is substantially undoped, the transistor may be formed such that the junction capacitance between the source/drain regions and the underlying region is reduced. If desired, the epitaxial layer, or a portion thereof, may be doped to decrease the resistance between the channel region and the well contact.
    Type: Application
    Filed: September 26, 2005
    Publication date: March 29, 2007
    Inventors: Richard Lindsay, Phung Nguyen, Jeong-Hwan Yang
  • Publication number: 20050088186
    Abstract: Disclosed is an on-chip test device for testing the thickness of gate oxides in transistors. A ring oscillator provides a ring oscillator output and an inverter receives the ring oscillator output as an input. The inverter is coupled to a gate oxide and the inverter receives different voltages as power supplies. The difference between the voltages provides a measurement of capacitance of the gate oxide. The difference between the voltages is less than or equal to approximately one-third of the difference between a second set of voltages provided to the ring oscillator. The capacitance of the gate oxide comprises the inverse of the frequency of the ring oscillator output multiplied by the difference between the voltages, less a capacitance constant for the test device. This capacitance constant is for the test device alone, and does not include any part of the capacitance of the gate oxide. The measurement of capacitance of the gate oxide is used to determine the thickness of the gate oxide.
    Type: Application
    Filed: October 22, 2003
    Publication date: April 28, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edward Maciejewski, Phung Nguyen, Edward Nowak