Patents by Inventor Phung T. Nguyen
Phung T. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8569840Abstract: A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.Type: GrantFiled: February 10, 2012Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Thomas A. Wallner, Ebenezer E. Eshun, Daniel J. Jaeger, Phung T. Nguyen
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Publication number: 20120139056Abstract: A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.Type: ApplicationFiled: February 10, 2012Publication date: June 7, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas A. Wallner, Ebenezer E. Eshun, Daniel J. Jaeger, Phung T. Nguyen
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Patent number: 8129234Abstract: A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.Type: GrantFiled: September 9, 2009Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Thomas A. Wallner, Ebenezer E. Eshun, Daniel J. Jaeger, Phung T. Nguyen
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Patent number: 8035126Abstract: A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.Type: GrantFiled: October 29, 2007Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Phung T. Nguyen, Robert C. Wong
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Publication number: 20110057266Abstract: A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.Type: ApplicationFiled: September 9, 2009Publication date: March 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas A. Wallner, Ebenezer E. Eshun, Daniel J. Jaeger, Phung T. Nguyen
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Patent number: 7803644Abstract: Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the measurement structure on the multiple chip wafer using a reticle including the measurement structure between copies of the multiple chips on the reticle, wherein no one of the multiple chips covers an entirety of the reticle; performing the test on the multiple chip wafer using the measurement structure to acquire data across the reticle; using data from the performing to establish an across reticle variation model; and using the across reticle variation model to predict across chip variation for at least one of the multiple chips.Type: GrantFiled: September 12, 2007Date of Patent: September 28, 2010Assignee: International Business Machines CorporationInventors: Bruce W. Balch, Jeanne P. Bickford, Nazmul Habib, Phung T. Nguyen
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Patent number: 7781797Abstract: A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.Type: GrantFiled: June 29, 2006Date of Patent: August 24, 2010Assignee: International Business Machines CorporationInventors: Phung T. Nguyen, Robert C. Wong
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Publication number: 20090108287Abstract: A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.Type: ApplicationFiled: October 29, 2007Publication date: April 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Phung T. Nguyen, Robert C. Wong
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Publication number: 20090068772Abstract: Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the measurement structure on the multiple chip wafer using a reticle including the measurement structure between copies of the multiple chips on the reticle, wherein no one of the multiple chips covers an entirety of the reticle; performing the test on the multiple chip wafer using the measurement structure to acquire data across the reticle; using data from the performing to establish an across reticle variation model; and using the across reticle variation model to predict across chip variation for at least one of the multiple chips.Type: ApplicationFiled: September 12, 2007Publication date: March 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce W. Balch, Jeanne P. Bickford, Nazmul Habib, Phung T. Nguyen
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Publication number: 20080029781Abstract: A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.Type: ApplicationFiled: June 29, 2006Publication date: February 7, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Phung T. Nguyen, Robert C. Wong
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Publication number: 20070293016Abstract: A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.Type: ApplicationFiled: June 14, 2006Publication date: December 20, 2007Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: Zhijiong Luo, Hung Y. Ng, Nivo Rovedo, Phung T. Nguyen, William C. Wille, Richard Lindsay, Zhao Lun, Yung Fu Chong, Siddhartha Panda
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Patent number: 6980009Abstract: Disclosed is an on-chip test device for testing the thickness of gate oxides in transistors. A ring oscillator provides a ring oscillator output and an inverter receives the ring oscillator output as an input. The inverter is coupled to a gate oxide and the inverter receives different voltages as power supplies. The difference between the voltages provides a measurement of capacitance of the gate oxide. The difference between the voltages is less than or equal to approximately one-third of the difference between a second set of voltages provided to the ring oscillator. The capacitance of the gate oxide comprises the inverse of the frequency of the ring oscillator output multiplied by the difference between the voltages, less a capacitance constant for the test device. This capacitance constant is for the test device alone, and does not include any part of the capacitance of the gate oxide. The measurement of capacitance of the gate oxide is used to determine the thickness of the gate oxide.Type: GrantFiled: October 22, 2003Date of Patent: December 27, 2005Assignee: International Business Machines CorporationInventors: Edward P. Maciejewski, Phung T. Nguyen, Edward J. Nowak
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Patent number: 6856031Abstract: A low cost SRAM (Static Random Access Memory) cell is disclosed with P well and N well contacts and preferably with a P+ diffusion crossing to ground. The SRAM cell is complete at the M2 metal level and has improved cell passgate leakage, functionality and fabrication yields. The SRAM cell comprises cross coupled pnp pull-up devices P1, P2 and npn pull-down devices N1, N2, with the P1, P2 devices being connected to the power supply VDD, and the N1, N2 devices being coupled through a P+ diffusion region to ground. A first passgate is coupled between a first bitline and the junction of the devices P1 and N1, with its gate coupled to a wordline, and a second passgate is coupled between a second bitline and the junction of devices P2 and N2, with its gate coupled to the wordline.Type: GrantFiled: February 3, 2004Date of Patent: February 15, 2005Assignee: International Business Machines CorporationInventors: Phung T. Nguyen, Robert C. Wong
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Patent number: 6797569Abstract: A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.Type: GrantFiled: May 19, 2003Date of Patent: September 28, 2004Assignee: International Business Machines CorporationInventors: David B. Colavito, Nivo Rovedo, Phung T. Nguyen
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Patent number: 6624486Abstract: A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.Type: GrantFiled: May 23, 2001Date of Patent: September 23, 2003Assignee: International Business Machines CorporationInventors: David B. Colavito, Nivo Rovedo, Phung T. Nguyen
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Publication number: 20030170941Abstract: A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.Type: ApplicationFiled: May 19, 2003Publication date: September 11, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David B. Colavito, Nivo Rovedo, Phung T. Nguyen
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Publication number: 20020175369Abstract: A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.Type: ApplicationFiled: May 23, 2001Publication date: November 28, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David B. Colavito, Nivo Rovedo, Phung T. Nguyen
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Patent number: 6373221Abstract: A charger coupling for charging a battery includes a paddle and a receptacle. The paddle and the receptacle exchange information by radio waves. The paddle includes waveguides for guiding radio waves between an antenna of the paddle and an antenna or the receptacle. The waveguides improve the radio communication between the paddle and the receptacle.Type: GrantFiled: December 27, 2000Date of Patent: April 16, 2002Assignees: Kabushiki Kaisha Toyoda Jidoshokki Seisakusho, General Motors CorporationInventors: Yasuhiro Koike, Karl David Conroy, Phung T. Nguyen
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Publication number: 20010035734Abstract: A charger coupling for charging a battery includes a paddle and a receptacle. The paddle and the receptacle exchange information by radio waves. The paddle includes waveguides for guiding radio waves between an antenna of the paddle and an antenna or the receptacle. The waveguides improve the radio communication between the paddle and the receptacle.Type: ApplicationFiled: December 27, 2000Publication date: November 1, 2001Inventors: Yasuhiro Koike, Karl David Conroy, Phung T. Nguyen
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Patent number: 5258640Abstract: An integrated gate and semiconductor barrier layer diode which functions as a regular diode when the gate is turned off and as, a Schottky barrier diode with the gate turned on.Type: GrantFiled: September 2, 1992Date of Patent: November 2, 1993Assignee: International Business Machines CorporationInventors: Chang-Ming Hsieh, Louis L. Hsu, Phung T. Nguyen, Lawrence F. Wagner, Jr.