Abstract: A method for memory protection in a multiprocessor system, involving receiving a request at a first carrier to perform a memory operation at a memory address, wherein the first carrier receives the request from a processor, determining by the first carrier whether the processor is permitted to access memory at the memory address using a carrier identification (ID) of a second carrier, wherein the second carrier is associated with a memory controller used to access the memory, and sending the request to the second carrier, if the processor is permitted to access the memory.

Abstract: A method for metadata management for scalable processes, involving creating a process by a first home processor, wherein the process is associated with a process identification (ID), storing the processor ID and information identifying the first home processor in a global process look-up data structure (GPLD), requesting metadata associated with the process, searching the GPLD to obtain the first home processor of the process using the process ID, and retrieving the metadata associated with the process from the first home processor.

Abstract: A system and method for allocating the nearest available physical memory in a distributed, shared memory system. In various embodiments, a processor node may broadcast a memory request to a first subset of nodes connected to it via a communication network. In some embodiments, if none of these nodes is able to satisfy the request, the processor node may broadcast the request to additional subsets of nodes. In some embodiments, each node of the first subset of nodes may be removed from the processor node by one network hop and each node of the additional subsets of nodes may be removed from the processor node by no more than an iteratively increasing number of network hops. In some embodiments, the processor node may send an acknowledgment to one node that can fulfill the request and a negative acknowledgement to other nodes that can fulfill the request.

Abstract: A method for detecting a dependence violation in an application that involves executing a plurality of sections of the application in parallel, and logging memory transactions that occur while executing the plurality of sections to obtain a plurality of logs and a plurality of temporary results, where the plurality of logs is compared while executing the plurality of sections to determine whether the dependence violation exists.

Abstract: The use of a token-based memory protection technique may provide memory protection in a computer system employing memory virtualization. A token-based memory protection technique may include assigning a unique identifier to an application, process, or thread, and associating the identifier with a block of memory allocated to that application, process, or thread. Subsequent to assigning the identifier, a packet requesting access to that block of memory may include a token to be compared to the identifier. A memory controller may be configured to associate the identifier with the block of memory and to compare the token in the memory request packet to the identifier before granting access. If a second block of memory is subsequently allocated to the application, process, or thread, the identifier may be disassociated with the first block of memory and associated with the second block of memory.

Abstract: A computer system may employ a first memory virtualization and corresponding virtual-to-physical address translation technique for a first application executing on a processor and a second memory virtualization and corresponding virtual-to-physical address translation technique for a second application executing on the same processor transparent to the first application. Different virtualization and corresponding translation techniques may be employed on a per-thread basis, rather than a per-application basis. Different virtualization and corresponding translation techniques may be employed for accesses to different ranges of virtual or corresponding physical addresses. Different virtualization and corresponding translation techniques may employ different page sizes. A first or second virtualization and corresponding translation technique may include page-based, segment-based, or function-based virtual-to-physical address translation.

Abstract: A method for executing a loop in an application that includes executing iterations in a first segment of the loop by a base thread, logging memory transactions that occur during execution of iterations in the first segment by a co-inspector thread to obtain a co-inspector log, executing iterations in a second segment of the loop by a co-thread to obtain temporary results, logging memory transactions that occur during execution of iterations in the second segment to obtain a co-thread log, and comparing the co-inspector log and the co-thread log to determine whether a thread interdependency exists.

Abstract: A computer system employing memory virtualization may employ a function-based technique for virtual-to-physical address translation. A function-based translation technique may involve replacing a generic trap handler and one or more translation table look-ups with a function to compute a corresponding physical address from a given virtual address. The computer system may be configured to determine a translation function dependent on mappings in one or more translation tables. The computer system may be configured to reorganize a memory, to reorganize one or more translation tables, or to allocate different blocks of memory to an application prior to determining a translation function. Different applications or threads executing on the computer system may employ different translation functions. Different regions of memory may be accessed using different translation functions. Some virtual addresses may be translated using a function while others may be translated using one or more translation table look-ups.

Abstract: A method for committing memory transactions in an application that includes executing a plurality of sections of the application in parallel, logging a plurality of memory transactions that occur while executing the plurality of sections to obtain a plurality of logs and a plurality of temporary results, wherein the plurality of memory transactions that includes a plurality of writes to at least one memory location, comparing the plurality of logs to identify an optimal list of writes from the plurality of writes, and committing memory transactions corresponding to a subset of the plurality of temporary results, wherein the subset of the plurality of temporary results is identified by the optimal list of writes.

Abstract: A computer system may be configured to dynamically select a memory virtualization and corresponding virtual-to-physical address translation technique during execution of an application and to dynamically employ the selected technique in place of a current technique without re-initializing the application. The computer system may be configured to determine that a current address translation technique incurs a high overhead for the application's current workload and may be configured to select a different technique dependent on various performance criteria and/or a user policy. Dynamically employing the selected technique may include reorganizing a memory, reorganizing a translation table, allocating a different block of memory to the application, changing a page or segment size, or moving to or from a page-based, segment-based, or function-based address translation technique.

Abstract: A system for mapping memory of a computer system includes a sorter, a partitioner, and a mapper. The sorter sorts a physical memory space to obtain a sorted virtual memory space, where the physical memory space includes a plurality of memory patterns, wherein each of the plurality of memory patterns is associated with a physical device and includes at least one memory block, wherein the at least one memory block is contiguous and addressable, and the plurality of memory patterns are arranged based on a predefined number of occurrences of each memory pattern, size of contiguous memory address ranges in each of the plurality of memory patterns, size of contiguous memory address ranges in each of the plurality of memory patterns, and arrangement of contiguous address ranges in each of the plurality of memory patterns.

Abstract: A method for accuracy-aware analysis of a program involving obtaining source code for the program comprising a floating point variable, instrumenting the source code to associate an accuracy-aware tracking structure with the floating-point variable to obtain instrumented source code, compiling to instrumented source code to obtain instrumented compiled code, and executing the instrumented compiled code, wherein executing the instrumented compiled code comprises using the accuracy-aware tracking structure to track an operation on the floating-point variable.

Abstract: A method for detecting a dependence violation in an application that involves executing a plurality of sections of the application in parallel, and logging memory transactions that occur while executing the plurality of sections to obtain a plurality of logs and a plurality of temporary results, where the plurality of logs is compared while executing the plurality of sections to determine whether the dependence violation exists.

Abstract: A system for mapping memory of a computer system includes a sorter, a partitioner, and a mapper. The sorter sorts a physical memory space to obtain a sorted virtual memory space, where the physical memory space includes a plurality of memory patterns, wherein each of the plurality of memory patterns is associated with a physical device and includes at least one memory block, wherein the at least one memory block is contiguous and addressable, and the plurality of memory patterns are arranged based on a predefined number of occurrences of each memory pattern, size of contiguous memory address ranges in each of the plurality of memory patterns, size of contiguous memory address ranges in each of the plurality of memory patterns, and arrangement of contiguous address ranges in each of the plurality of memory patterns.

Abstract: A method for committing memory transactions in an application that includes executing a plurality of sections of the application in parallel, logging a plurality of memory transactions that occur while executing the plurality of sections to obtain a plurality of logs and a plurality of temporary results, wherein the plurality of memory transactions that includes a plurality of writes to at least one memory location, comparing the plurality of logs to identify an optimal list of writes from the plurality of writes, and committing memory transactions corresponding to a subset of the plurality of temporary results, wherein the subset of the plurality of temporary results is identified by the optimal list of writes.

Abstract: A computer system may be configured to dynamically select a memory virtualization and corresponding virtual-to-physical address translation technique during execution of an application and to dynamically employ the selected technique in place of a current technique without re-initializing the application. The computer system may be configured to determine that a current address translation technique incurs a high overhead for the application's current workload and may be configured to select a different technique dependent on various performance criteria and/or a user policy. Dynamically employing the selected technique may include reorganizing a memory, reorganizing a translation table, allocating a different block of memory to the application, changing a page or segment size, or moving to or from a page-based, segment-based, or function-based address translation technique.

Abstract: The use of a token-based memory protection technique may provide memory protection in a computer system employing memory virtualization. A token-based memory protection technique may include assigning a unique identifier to an application, process, or thread, and associating the identifier with a block of memory allocated to that application, process, or thread. Subsequent to assigning the identifier, a packet requesting access to that block of memory may include a token to be compared to the identifier. A memory controller may be configured to associate the identifier with the block of memory and to compare the token in the memory request packet to the identifier before granting access. If a second block of memory is subsequently allocated to the application, process, or thread, the identifier may be disassociated with the first block of memory and associated with the second block of memory.

Abstract: A computer system may employ a first memory virtualization and corresponding virtual-to-physical address translation technique for a first application executing on a processor and a second memory virtualization and corresponding virtual-to-physical address translation technique for a second application executing on the same processor transparent to the first application. Different virtualization and corresponding translation techniques may be employed on a per-thread basis, rather than a per-application basis. Different virtualization and corresponding translation techniques may be employed for accesses to different ranges of virtual or corresponding physical addresses. Different virtualization and corresponding translation techniques may employ different page sizes. A first or second virtualization and corresponding translation technique may include page-based, segment-based, or function-based virtual-to-physical address translation.

Abstract: A computer system employing memory virtualization may employ a function-based technique for virtual-to-physical address translation. A function-based translation technique may involve replacing a generic trap handler and one or more translation table look-ups with a function to compute a corresponding physical address from a given virtual address. The computer system may be configured to determine a translation function dependent on mappings in one or more translation tables. The computer system may be configured to reorganize a memory, to reorganize one or more translation tables, or to allocate different blocks of memory to an application prior to determining a translation function. Different applications or threads executing on the computer system may employ different translation functions. Different regions of memory may be accessed using different translation functions. Some virtual addresses may be translated using a function while others may be translated using one or more translation table look-ups.