Abstract: Utilizing an asymmetric magnetic field caused by a mechanism design between a motor rotor and a stator to induce a BEMF, a method for starting a fixed rotation direction of single-phase sensorless DC brushless motor, includes: power-on starting a motor control circuit; if the motor is not in a rotating state before starting the excitation, executing a static starting procedure; then, if the motor rotation direction conforms to a predetermined direction, executing a normal driving procedure; otherwise, executing a static starting procedure. The static starting procedure, by discharging remnant energy of the motor, achieves the purpose of star-up by performing the steps of first phase excitation, stop excitation, and strong second phase excitation. In the normal driving procedure, the slope of BEMF signal of the first phase or the second phase is taken out periodically to detect the motor rotation direction.

Abstract: The invention utilizes an asymmetric magnetic field caused by a mechanism design between a motor rotor and a stator to induce a BEMF, and discloses a method for starting a fixed rotation direction of single-phase sensorless DC brushless motor, including: power-on starting a motor control circuit; if the motor not in the rotating state before starting the excitation, executing a static starting procedure; then, if the motor rotation direction conforming to the predetermined direction, executing a normal driving procedure; otherwise, executing a static starting procedure. The static starting procedure, after of static starting by discharging remnant energy of the motor, achieves the purpose of star-up by performing the steps of first phase excitation, stop excitation, and strong second phase excitation. In the normal driving procedure, the slopes of BEMF signal of the first phase or the second phase is taken out periodically to detect the motor rotation direction.

Abstract: The invention discloses a driving method for single-phase DC brushless motor using sensor only in start-up, comprising: power-up to activate a motor control circuit of a motor; confirming whether the motor is in a rotating state before activation of an excitation? If not, executing a static start-up procedure of using a sensor to detect magnetic poles of the rotor; calculating slope of the BEMF signal to determine the rotation direction of the motor; determining whether the rotation direction of the motor conforming to a predetermined direction; if yes, executing a normal driving procedure; otherwise, executing the static start-up procedure of using a sensor to detect magnetic poles of the rotor. The invention utilizes the present invention utilizes an asymmetric magnetic field caused by a mechanism between a rotor and a stator of a motor to induce a back electromotive force signal and a sensor detection to control rotation direction.

Abstract: A computing system supports a clearance mode for its processor cores. The computing system can transition a target processor core from an active mode into a clearance mode according to a system policy. The system policy determines the number of processor cores to be in the active mode. The transitioning into the clearance mode includes the operations of migrating work from the target processor core to one or more other processor cores in the active mode in the computing system; and removing the target processor core from a scheduling configuration of the computing system to prevent task assignment to the target processor core. When the target processor core is in the clearance mode, the target processor core is maintained in an online idle state in which the target processor core performs no work.

Abstract: A method of fabricating integrated circuits includes the steps of: a) with reference to a physical design of a hardware unit, preparing an integrated circuit component mask layout set associated with component photomasks suitable for fabricating an array of the hardware units on a wafer; b) preparing the component photomasks with reference to the integrated circuit component mask layout set; c) forming the array of the hardware units and interconnections between adjacent hardware units on the wafer using the component photomasks prepared in step b) ; and d) cutting the wafer along selected ones of the scribe lines so as to form a plurality of integrated circuit dies. Each of the integrated circuit dies is independently selected from a single-type including only one of the hardware units, and a multi-type including a plurality of the hardware units that are interconnected electrically via uncut ones of the conductive paths.

Abstract: A method of fabricating integrated circuits includes the steps of: a) with reference to a physical design of a hardware unit, preparing an integrated circuit component mask layout set associated with component photomasks suitable for fabricating an array of the hardware units on a wafer; b) preparing the component photomasks with reference to the integrated circuit component mask layout set; c) forming the array of the hardware units and interconnections between adjacent hardware units on the wafer using the component photomasks prepared in step b) ; and d) cutting the wafer along selected ones of the scribe lines so as to form a plurality of integrated circuit dies. Each of the integrated circuit dies is independently selected from a single-type including only one of the hardware units, and a multi-type including a plurality of the hardware units that are interconnected electrically via uncut ones of the conductive paths.

Abstract: The invention discloses a centralized computer system, i.e., so-called blade PC system. The centralized computer system according to the invention includes a plurality of centralized and bladed hosts and a plurality of I/O peripherals. In particularly, the centralized computer system according to the invention is capable of automatically detecting a current status of each host and/or each set of I/O peripherals.

Abstract: The invention discloses a centralized computer system, i.e., so-called blade PC system. The centralized computer system according to the invention includes a plurality of centralized and bladed hosts and a plurality of I/O peripherals. In particularly, the centralized computer system according to the invention is capable of pairing the hosts and the I/O peripherals.

Abstract: The invention is to provide a centralized computer system, i.e., so-called blade PC system. The centralized computer system according to the invention includes a plurality of centralized and bladed hosts. In particularly, the centralized computer system according to the invention enables a set of I/O peripherals to operate a host or a host switch connecting with the host to execute specific functions in a hot key way.

Abstract: The invention discloses a centralized computer system, i.e., so-called blade PC system. The centralized computer system according to the invention includes a plurality of centralized and bladed hosts and a plurality of I/O peripherals. In particularly, the centralized computer system according to the invention is capable of automatically detecting a current status of each host and/or each set of I/O peripherals.

Abstract: The wireless network apparatus is electrically connected to a CPU, and comprises a hard-wired computing module and a transmitting module. The CPU executes a driver software to compute a first PLCP length for a first transmission rate, while the wireless network apparatus converts the first PLCP length into a second PLCP length for a second transmission rate through one shift operation and one increment (or decrement) operation executed by the hard-wired computing module. According to the present invention method for transmitting data, the first PLCP length of the first transmission rate is computed first, and the data is then transmitted at the first transmission rate. If the transmission at the first transmission rate fails, the hard-wired computing module will compute the second PLCP length for the second transmission rate based on the first PLCP length, and then the data is transmitted again at the second transmission rate.

Abstract: A transformation device for remote monitoring a computer display image is described. The transformation device monitors display images of a server on a remote computer display via a network. The transformation device includes an image capture unit and a system-on-chip. The image capture unit captures the display images from the a display cable and transforms the display images into digital image data fulfilling browser safe palette requirements and corresponding synchronization signals to reduce the bandwidth requirements. The system-on-chip transforms the digital image data and the corresponding synchronization signals into network packets and delivers the network packets to the remote computer so as to display instantly the display images of the server on a display of the remote computer.

Abstract: A virtual disc drive control device is described. The control device controls a remote disc drive for a local computer via a network. The control device includes an input/output interface, a virtual disc drive simulation firmware, and a network interface controller. The input/output interface receives information from the local computer. The firmware simulates a local disc drive and responses the information. The firmware responds to the information if the firmware is able to answer directly the information. The firmware sends the information to a remote computer if the firmware is not able to answer the information. A remote disc drive agent of the remote computer controls a remote disc drive according the information and responds to the information. The firmware simulates a local disc drive response according to the remote computer response and sends the local disc drive response to the local computer.

Abstract: A virtual keyboard and mouse control device is described. The control device controls a server with a keyboard and a mouse of a remote computer via a network. The control device includes an input interface, a transformation device, a first output interface and a second output interface. The input interface receives packets from the remote computer via the network. The transformation device transforms the packets into mouse output signals and keyboard output signals according to the input specification of the server to simulate a local keyboard and a local mouse. The first output interface sends the keyboard output signals to the server and the second output interface sends the mouse output signals to the server. The first and second output interface includes a universal serial bus, an IEEE 1394 bus or a PS/2 input/output port.

Abstract: A piecewise linear phase locked loop frequency generator generates a voltage signal controlled by an input voltage. This frequency generator has a variable static frequency generator, whose frequency is selected by a control voltage and whose transfer function between control voltage and output frequency is further selected by a piecewise linear determination parameter. The piecewise linear determination parameter is the number which selects which portion of the frequency spectrum is being represented by the control voltage to frequency transfer function being selected and is a function of an input control voltage. The frequency generator has a set of n low pass filters, used to work in conjunction with the corresponding control voltage to provide frequency transfer functions which are selected by the piecewise linear determination parameter.

Abstract: In the present invention a method is described to produce a whole chip timing verification that includes the effects of voltage variation on delay. This is done by creating a netlist, defining cell input and output (I/O) delay paths, and calculating the difference timing caused by differences in power supply voltage. The incremental I/O path delay is calculated by adding delay changes caused by all power pins. Whole chip timings are generated without consideration to voltage drops and then modified using the incremental path delay. The modified whole chip timing data file is used with traditional timing verification tools to perform a whole chip cell level timing verification.