Abstract: A dynamic random access memory (DRAM) cell is disclosed. First, a dual damascene trench is formed in a silicon substrate, and the dual damascene trench is composed of an upper first trench and a lower second trench. Then, a buried plate is formed in the silicon substrate to surround the second trench. A node dielectric is formed on a surface of the buried plate, and a collar dielectric is formed on portions of the silicon substrate in the second trench. A buried strap is formed in the second trench, and a trench top oxide (TTO) is formed on the buried strap. Finally, a threshold voltage of a metal oxide semiconductor (MOS) transistor of the memory cell is adjusted, and a source, a drain and a gate of the MOS transistor are formed.