Abstract: The present invention provides a battery charger and a method for preventing both an overshoot charging current and an overcharged battery voltage during a mode transition. The battery charger includes a charging regulation circuit having an input terminal, an output terminal, and a control terminal, wherein the charging regulation circuit outputs a charging current whose amount is regulated based on a first regulation signal at the control terminal; an operational amplifier having a positive input terminal, a negative input terminal, and an output terminal for generating the first regulation signal; a first switch unit; and a second switch unit.

Abstract: The invention provides a peak detector having input signal triggering control and low frequency energy attenuation capability. The peak detector includes a charging unit and a discharging unit. By being triggered by a peak value detected in a received input signal by comparing voltage potential levels of the output signal of the peak detector and the received signal, the charging unit charges an electrical charge storage unit, for example, a capacitor, connected to the output terminal of the peak detector for a pre-determined charge duration in accordance with a charge pulse being in a logic high. After the pre-determined charge duration of charging operation, before being triggered by a next peak value of the received input signal, the discharging unit discharges the electrical charge storage unit for a pre-determined discharge duration in accordance with a discharge pulse being in a logic high or in accordance with a plurality of discharge pulses, which is determined by design desired.

Abstract: An open-loop data recovery apparatus and method utilizing an oversampling technique is provided, by which the occurrence of data transitions is counted and a proper sampling clock phase is decided. Counters with variable thresholds are used to monitor the occurrence of phase transitions for a phase selection circuit to determine a preferred phase for recovery of sampled data. The thresholds of the counters are further adjusted in reference with the preferred phase decided by the phase selection circuit.

Abstract: In the present invention, a transmission line length estimation circuit with continuous feedback equalizer is provided. The transmission line length estimation circuit comprises a DC bias circuit and a peak detector circuit to generate a DC voltage according to a different cable length. An equalizer core circuit is for receiving the first signal and generating a second signal. A peak detector circuit is used for the first signal and the second signal. A transmission line length detector circuit is coupled to the peak detector circuit and used for generating a plurality of first parameters for phase shift and amplitude losses according to the different cable length. An internal pattern calibration circuit is multiplexed to the first signal and used for generating a plurality of second parameters for calibration of close loop.

Abstract: The invention provides a peak detector having input signal triggering control and low frequency energy attenuation capability. The peak detector includes a charging unit and a discharging unit. By being triggered by a peak value detected in a received input signal by comparing voltage potential levels of the output signal of the peak detector and the received signal, the charging unit charges an electrical charge storage unit, for example, a capacitor, connected to the output terminal of the peak detector for a pre-determined charge duration in accordance with a charge pulse being in a logic high. After the pre-determined charge duration of charging operation, before being triggered by a next peak value of the received input signal, the discharging unit discharges the electrical charge storage unit for a pre-determined discharge duration in accordance with a discharge pulse being in a logic high or in accordance with a plurality of discharge pulses, which is determined by design desired.

Abstract: A peak detector comprising of a comparator, an input-trigger device, a gate-width control block, an AND gate, a first current source, a second current source, a first switch, a second switch and a capacitor. The peak detector of this invention uses simple circuits to obtain low frequency energy attenuation. The low frequency attenuation can be programmed and hence able to find the actual average voltage peak. In addition, the simple design makes the peak detector of this invention a suitable replacement candidate for the complicated analogue-to-digital converter conventionally used for detecting average energy attenuation after passing through an electric cable. The peak detector can also be used to measure voltage attenuation for signals passing through LAN, transmission medium such as cable or twisted pair or other related products.

Abstract: In the present invention, a transmission line length estimation circuit with continuous feedback equalizer is provided. The transmission line length estimation circuit comprises a DC bias circuit and a peak detector circuit to generate a DC voltage according to a different cable length. An equalizer core circuit is for receiving the first signal and generating a second signal. A peak detector circuit is used for the first signal and the second signal. A transmission line length detector circuit is coupled to the peak detector circuit and used for generating a plurality of first parameters for phase shift and amplitude losses according to the different cable length. An internal pattern calibration circuit is multiplexed to the first signal and used for generating a plurality of second parameters for calibration of close loop.

Abstract: A clock duty cycle control circuit comprises a reference voltage circuit and a constant current generator connected to the reference voltage circuit. A duty-cycle adjustment circuit is used to receive a clock signal and controlled by the bias voltage of the bias voltage generating circuit which is connected to constant current generator. Accordingly, by a method of controlling duty-cycle adjustment circuit, the bias voltage has capability for adjusting a charging time and a discharging time of the clock signal. Finally, an open-drain driver with open-drain output is connected to the duty-cycle adjustment circuit, and thereby substantially stabilizing the output duty cycle of the clock signal.

Abstract: A peak detector comprising of a comparator, an input-trigger device, a gate-width control block, an AND gate, a first current source, a second current source, a first switch, a second switch and a capacitor. The peak detector of this invention uses simple circuits to obtain low frequency energy attenuation. The low frequency attenuation can be programmed and hence able to find the actual average voltage peak. In addition, the simple design makes the peak detector of this invention a suitable replacement candidate for the complicated analogue-to-digital converter conventionally used for detecting average energy attenuation after passing through an electric cable. The peak detector can also be used to measure voltage attenuation for signals passing through LAN, transmission medium such as cable or twisted pair or other related products.