Abstract: A packet buffer stores packet data of packets received by a master device. The packet buffer includes a non-guaranteed buffer, a guaranteed buffer, and a reserved buffer. The non-guaranteed buffer is visible to the master device, and is not guaranteed to provide one free cell space for one cell in a first-type packet before the non-guaranteed buffer is full. The guaranteed buffer is visible to the master device, and is guaranteed to provide one free cell space for one cell in a second-type packet before the guaranteed buffer is full. The reserved buffer is invisible to the master device, and is arranged to provide headroom for the guaranteed buffer.

Abstract: A method for detecting capacitance values of a plurality of capacitive sensing nodes located at intersections of a plurality of drive lines and a sense line on a touch panel is provided. The method includes at least the following steps: obtaining a plurality of touch sense signals corresponding to the sense line during a plurality of time slots, respectively; demodulating the touch sense signals with a first oscillation signal to generate a plurality of first demodulated signals; demodulating the touch sense signals with a second oscillation signal to generate a plurality of second demodulated signals, wherein the second oscillation signal is different from the first oscillation signal; and determining the capacitance values according to at least the first demodulated signals and the second demodulated signals.

Abstract: A method for detecting capacitance values of a plurality of capacitive sensing nodes located at intersections of a plurality of drive lines and a sense line on a touch panel is provided. The method includes at least the following steps: obtaining a plurality of touch sense signals corresponding to the sense line during a plurality of time slots, respectively; demodulating the touch sense signals with a first oscillation signal to generate a plurality of first demodulated signals; demodulating the touch sense signals with a second oscillation signal to generate a plurality of second demodulated signals, wherein the second oscillation signal is different from the first oscillation signal; and determining the capacitance values according to at least the first demodulated signals and the second demodulated signals.

Abstract: An error correction method for correcting an first ECC code from a storage unit, comprising: (a) marking at least a first part of the first ECC code according to a correction result generated by correcting error of the first ECC code, to generate a first error correction reference information; and (b) marking at least a second part of the first ECC code according to the first error correction reference information to generate a second error correction reference information.

Abstract: A controller of an optical storage apparatus for generating a plurality of control signals is provided. The controller includes a code generator implemented for determining a plurality of control codes according to an input data associated with data recording, and generating the control signals to deliver the control codes. Each of the control codes represents one power level. Besides, regarding each of the control signals, a minimum transmission pulse length thereof corresponds to more than one power symbol period.

Abstract: A method for tuning a write strategy parameter of an optical storage device, includes: writing a segment of data according to a plurality of write strategies; reading the data back and detecting a plurality of lengths, each length corresponding to a pit or a land on an optical storage medium accessed by the optical storage device; performing calculations according to the lengths and a plurality of data types to generate a plurality of calculation results, each of the data types corresponding to at least a specific target pit length or at least a specific target land length; and utilizing the calculation results to determine a proper write strategy.

Abstract: A signal pattern detecting apparatus, which is capable of detecting a physical mark in a read back signal being read from an optical disc, includes a matching signal generator, a signal comparing device, and a decision circuit. The matching signal generator is utilized for generating a matching signal, capable of being utilized to identify the physical mark, according to a reference clock and a wobble clock. The signal comparing device is electrically connected to the matching signal generator, and utilized for comparing the matching signal with a wobble data signal to generate a comparison signal. The decision circuit is electrically connected to the signal comparing device, and utilized for generating an indication signal according to the comparison signal and a threshold value. Both the wobble data signal and the wobble clock are derived from the read back signal.

Abstract: An address-accessing device includes first and second information generators for producing first and second information according to the received address signals; a phase offset detector for producing a phase offset according to the first and second information; a reference signal generator for producing a reference signal according to the phase offset, the first information and the second information; and a decoder used to determine the structure type of an address-in-pregroove unit (ADIP) according to the reference value. This address-accessing device is capable of adjusting the decision level and the phase offset automatically to lower the error rate occurring in the address access procedure.

Abstract: An apparatus for maximum likelihood signal detection comprises a reference data unit, a branch metric unit, an add-compare-select unit, a path metric unit and a path memory, and is used for detecting maximum likelihood signal. The reference information unit, the branch metric unit, the add-compare-select unit or the path metric unit can further comprise a multiplexer to removing unnecessary paths according to a control signal. The control signal is adjusted according to channel response, coding constraint or channel memory length.

Abstract: An address-accessing device includes first and second information generators for producing first and second information according to the received address signals; a phase offset detector for producing a phase offset according to the first and second information; a reference signal generator for producing a reference signal according to the phase offset, the first information and the second information; and a decoder used to determine the structure type of an address-in-pregroove unit (ADIP) according to the reference value. This address-accessing device is capable of adjusting the decision level and the phase offset automatically to lower the error rate occurring in the address access procedure.

Abstract: A method for improving readability of an optical disc includes: changing a first control parameter of an optical storage apparatus that accesses the optical disc and obtaining a plurality of associated values of an index corresponding to the readability of the optical disc for respective changed/unchanged values of the first control parameter; setting the first control parameter to be an optimal value out of the changed/unchanged values of the first control parameter according to the index; changing a second control parameter with the first parameter set to be the optimal value to obtaining a plurality of associated values of the index for respective changed/unchanged values of the second control parameter; and setting the second control parameter to be an optimal value according to the index. The control parameters having their individual optimal values are utilized for further control during decoding. In addition, an associated optical storage apparatus is further provided.

Abstract: An address-accessing device includes first and second information generators for producing first and second information according to the received address signals; a phase offset detector for producing a phase offset according to the first and second information; a reference signal generator for producing a reference signal according to the phase offset, the first information and the second information; and a decoder used to determine the structure type of an address-in-pregroove unit (ADIP) according to the reference value. This address-accessing device is capable of adjusting the decision level and the phase offset automatically to lower the error rate occurring in the address access procedure.

Abstract: The invention discloses an error-correcting apparatus for decoding an input signal by using a Viterbi algorithm to generate a Viterbi-decoded signal, including an erasure unit and a decoder. The erasure unit is configured to generate at least one logic signal according to at least one path metric difference of path metrics in the Viterbi algorithm, and generate erasure information, wherein the erasure information indicates data reliability of at least one location of the Viterbi-decoded signal. The decoder is configured to decode the Viterbi-decoded signal according to the erasure information.

Abstract: An apparatus for maximum likelihood signal detection comprises a reference data unit, a branch metric unit, an add-compare-select unit, a path metric unit and a path memory, and is used for detecting maximum likelihood signal. The reference information unit, the branch metric unit, the add-compare-select unit or the path metric unit can further comprise a multiplexer to removing unnecessary paths according to a control signal. The control signal is adjusted according to channel response, coding constraint or channel memory length.

Abstract: An apparatus for generating Viterbi-processed data using an input signal obtained from reading an optical disc includes a Viterbi decoding unit and a control circuit. The Viterbi decoding unit is arranged to process the input signal and generate the Viterbi-processed data. In addition, the control circuit is arranged to control at least one component of the apparatus based upon at least one signal within the apparatus. Additionally, the component includes a phase locked loop (PLL) processing unit, an equalizer, and/or the Viterbi decoding unit. An associated apparatus including an equalizer and a Viterbi module is further provided. An associated apparatus including a Viterbi decoding unit and a control circuit is also provided. An associated apparatus including an equalizer, at least one offset/gain controller, and a Viterbi module is further provided. An associated apparatus including an equalizer, a Viterbi module, and a peak/bottom/central (PK/BM/DC) detector is also provided.

Abstract: The invention discloses an apparatus for generating a Viterbi-processed data using an input signal obtained from an optical disk, including a Viterbi module and a binary signal enhancing module. The Viterbi module is configured to process the input signal according to a binary signal. The binary signal enhancing module is configured to boost the input signal and generate the binary signal accordingly.

Abstract: A controller of an optical storage apparatus for generating a plurality of control signals is provided. The controller includes a code generator implemented for determining a plurality of control codes according to an input data associated with data recording, and generating the control signals to deliver the control codes. Each of the control codes represents one power level. Besides, regarding each of the control signals, a minimum transmission pulse length thereof corresponds to more than one power symbol period.

Abstract: An apparatus for maximum likelihood signal detection comprises a reference data unit, a branch metric unit, an add-compare-select unit, a path metric unit and a path memory, and is used for detecting maximum likelihood signal. The reference information unit, the branch metric unit, the add-compare-select unit or the path metric unit can further comprise a multiplexer to removing unnecessary paths according to a control signal. The control signal is adjusted according to channel response, coding constraint or channel memory length.

Abstract: A path metric computing method applied in a high-speed Viterbi detector and related apparatus thereof are disclosed. The path metric computing apparatus includes a comparator for generating a control signal according a plurality of previous path metrics, a combining circuit for generating a plurality of first output values according to the previous path metrics and branch costs of a plurality of branches of a current state, and a multiplexer, electrically connected to the comparator and the combining circuit, for determining a first path metric of the current state according to the control signal and the output values.

Abstract: An error correction method for correcting an first ECC code from a storage unit, comprising: (a) marking at least a first part of the first ECC code according to a correction result generated by correcting error of the first ECC code, to generate a first error correction reference information; and (b) marking at least a second part of the first ECC code according to the first error correction reference information to generate a second error correction reference information.