Patents by Inventor Pi-Hsuan Lai

Pi-Hsuan Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10224324
    Abstract: A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: March 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsin Liu, Pi-Hsuan Lai
  • Publication number: 20170345819
    Abstract: A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.
    Type: Application
    Filed: August 21, 2017
    Publication date: November 30, 2017
    Inventors: Wei-Hsin Liu, Pi-Hsuan Lai
  • Publication number: 20170309621
    Abstract: A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.
    Type: Application
    Filed: April 22, 2016
    Publication date: October 26, 2017
    Inventors: Wei-Hsin Liu, Pi-Hsuan Lai
  • Patent number: 9793267
    Abstract: A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: October 17, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsin Liu, Pi-Hsuan Lai
  • Patent number: 9530696
    Abstract: A method of fabricating a semiconductor device is provided. A plurality of sacrificial gates and a plurality of sacrificial gate dielectric layers thereunder are formed on a substrate. An interlayer dielectric layer is filled between the sacrificial gates. A protective layer is formed on the interlayer dielectric layer. The sacrificial gates and the sacrificial gate dielectric layers are removed to form an opening, wherein the interlayer dielectric layer is protected by the protective layer from recessing. A stacked gate structure is formed in the opening, wherein the protective layer is removed.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: December 27, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Hsin Liu, Fu-Yu Tsai, Bin-Siang Tsai, Wei-Lun Hsu, Shang-Yi Yang, Pi-Hsuan Lai