Patents by Inventor Pi-Kuang Chuang
Pi-Kuang Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240128313Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.Type: ApplicationFiled: October 17, 2022Publication date: April 18, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Tse-Hsiao LIU, Chih-Wei LIN, Po-Hao CHIU, Pi-Kuang CHUANG, Ching-Yi HSU
-
Patent number: 11158533Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first trench, and a second trench. The substrate has a first region and a second region. The first trench is formed in the substrate within the first region. The first trench is surrounded by a first protrusion structure having a top portion and sidewalls. The second trench is formed in the substrate within the second region. The second trench is surrounded by a second protrusion structure having a top portion and sidewalls. The second trench is deeper than the first trench. The connection portion between the top portion and the sidewalls of the second protrusion structure has a greater radius of curvature than the connection portion between the top portion and the sidewalls of the first protrusion structure.Type: GrantFiled: November 7, 2018Date of Patent: October 26, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Ching-Yi Hsu, Pi-Kuang Chuang, Po-Sheng Hu
-
Publication number: 20200176600Abstract: A high-voltage semiconductor device is provided. The high-voltage semiconductor device includes a substrate. The high-voltage semiconductor device also includes a first well region, a second well region and a third well region which are disposed within the substrate. The first well region is separated from the second well region by the third well region. The first well region and the second well region have a second conductive type, and the third well region has the first conductive type. The high-voltage semiconductor device further includes a source region and a drain region which are respectively disposed in the first well region and the second well region. In addition, the high-voltage semiconductor device includes a gate structure disposed over the substrate. The high-voltage semiconductor device also includes a first doped region embedded in the third well region, wherein the first doped region has the second conductive type.Type: ApplicationFiled: December 3, 2018Publication date: June 4, 2020Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Wei LIN, Pi-Kuang CHUANG
-
Publication number: 20200144101Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first trench, and a second trench. The substrate has a first region and a second region. The first trench is formed in the substrate within the first region. The first trench is surrounded by a first protrusion structure having a top portion and sidewalls. The second trench is formed in the substrate within the second region. The second trench is surrounded by a second protrusion structure having a top portion and sidewalls. The second trench is deeper than the first trench. The connection portion between the top portion and the sidewalls of the second protrusion structure has a greater radius of curvature than the connection portion between the top portion and the sidewalls of the first protrusion structure.Type: ApplicationFiled: November 7, 2018Publication date: May 7, 2020Applicant: Vanguard International Semiconductor CorporationInventors: Ching-Yi HSU, Pi-Kuang CHUANG, Po-Sheng HU
-
Patent number: 10418282Abstract: A method for forming an isolation structure of a semiconductor device is provided. The method includes forming a patterned dielectric structure in a first area and a second area of a substrate; forming a first isolation structure in the first area and forming a second isolation structure in the second area of the substrate; forming a cap layer over the first area and the second area of the substrate and performing an etching process to etch the cap layer of the second area completely; and performing an oxidation process on the second area to form a first oxide region over the second isolation structure and under the bottom surface of the patterned dielectric structure of the second area.Type: GrantFiled: May 9, 2018Date of Patent: September 17, 2019Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Pi-Kuang Chuang, Ching-Yi Hsu, Po-Sheng Hu
-
Publication number: 20180261509Abstract: A method for forming an isolation structure of a semiconductor device is provided. The method includes forming a patterned dielectric structure in a first area and a second area of a substrate; forming a first isolation structure in the first area and forming a second isolation structure in the second area of the substrate; forming a cap layer over the first area and the second area of the substrate and performing an etching process to etch the cap layer of the second area completely; and performing an oxidation process on the second area to form a first oxide region over the second isolation structure and under the bottom surface of the patterned dielectric structure of the second area.Type: ApplicationFiled: May 9, 2018Publication date: September 13, 2018Applicant: Vanguard International Semiconductor CorporationInventors: Pi-Kuang CHUANG, Ching-Yi HSU, Po-Sheng HU
-
Patent number: 9997410Abstract: A method for forming an isolation structure of a semiconductor device is provided. The method includes forming a patterned dielectric structure in a first area and a second area of a substrate; forming a first isolation structure in the first area and forming a second isolation structure in the second area of the substrate; forming a cap layer over the first area and the second area of the substrate and performing an etching process to etch the cap layer of the second area completely; and performing an oxidation process on the second area to form a first oxide region over the second isolation structure and under the bottom surface of the patterned dielectric structure of the second area.Type: GrantFiled: November 29, 2016Date of Patent: June 12, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Pi-Kuang Chuang, Ching-Yi Hsu, Po-Sheng Hu
-
Publication number: 20180151443Abstract: A method for forming an isolation structure of a semiconductor device is provided. The method includes forming a patterned dielectric structure in a first area and a second area of a substrate; forming a first isolation structure in the first area and forming a second isolation structure in the second area of the substrate; forming a cap layer over the first area and the second area of the substrate and performing an etching process to etch the cap layer of the second area completely; and performing an oxidation process on the second area to form a first oxide region over the second isolation structure and under the bottom surface of the patterned dielectric structure of the second area.Type: ApplicationFiled: November 29, 2016Publication date: May 31, 2018Applicant: Vanguard International Semiconductor CorporationInventors: Pi-Kuang CHUANG, Ching-Yi HSU, Po-Sheng HU
-
Patent number: 9660073Abstract: A high-voltage semiconductor device is provided. The device includes a semiconductor substrate including a well region of a first conductivity type and an isolation structure in the well region. First and second regions are respectively defined on both sides of the isolation structure. First and second gate structures are respectively disposed on the first and second regions. First and second implant regions of a second conductivity type that is different from the first conductivity type are respectively in the first and second regions and adjacent to the isolation structure. A counter implant region is in the well region under the isolation structure and laterally extends under the first and second implant regions. The counter implant region has the first conductivity type and has a doping concentration that is greater than that of the well region. A method for fabricating the high-voltage semiconductor device is also disclosed.Type: GrantFiled: December 17, 2015Date of Patent: May 23, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chih-Wei Lin, Pi-Kuang Chuang, Chao-Wei Wu
-
Patent number: 9219012Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.Type: GrantFiled: November 11, 2011Date of Patent: December 22, 2015Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang
-
Patent number: 8803234Abstract: A high voltage (HV) semiconductor device includes: a semiconductor substrate having a first conductivity type; a gate structure disposed over a portion of the semiconductor substrate; a pair of spacers respectively disposed over a sidewall of the gate structure, wherein one of the spacers is a composite spacer comprising a first insulating spacer contacting the gate structure, a dummy gate structure, and a second insulating spacer; a first drift region disposed in a portion of the semiconductor, underlying a portion of the gate structure and one of the pair of spacers, having a second conductivity type opposite to the first conductivity type; and a pair of doping regions, respectively disposed in a portion of the semiconductor substrate on opposite sides of the gate structure, wherein the pair of doping regions include the second conductivity type and one of the doping regions is disposed in the first drift region.Type: GrantFiled: March 18, 2013Date of Patent: August 12, 2014Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Cherng Liao, Yun-Chou Wei, Pi-Kuang Chuang, Ching-Yi Hsu, Chih-Wei Lin, Wen-Chung Chen, Che-Hua Chang, Yung-Lung Chou, Chung-Te Chou, Cheng-Lun Cho, Ya-Han Liang
-
Publication number: 20120056295Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.Type: ApplicationFiled: November 11, 2011Publication date: March 8, 2012Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: CHIH-PING LIN, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang
-
Patent number: 8080455Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.Type: GrantFiled: July 22, 2008Date of Patent: December 20, 2011Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang
-
Patent number: 8063439Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.Type: GrantFiled: November 23, 2010Date of Patent: November 22, 2011Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
-
Publication number: 20110062500Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.Type: ApplicationFiled: November 23, 2010Publication date: March 17, 2011Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
-
Patent number: 7863147Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.Type: GrantFiled: July 22, 2008Date of Patent: January 4, 2011Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
-
Publication number: 20100181639Abstract: A semiconductor device is provided. The semiconductor device comprises an epitaxial layer disposed on a semiconductor substrate, a plurality of electronic devices disposed on the epitaxial layer and a trench isolation structure disposed between the electric devices. The trench isolation structure comprises a trench in the epitaxial layer and the semiconductor substrate, an oxide liner on the sidewall and bottom of the trench, and a doped polysilicon layer filled in the trench. Moreover, a zero bias voltage can be applied to the doped polysilicon layer. The trench isolation structure can be used for isolating electronic devices having different operation voltages or high-voltage devices.Type: ApplicationFiled: January 19, 2009Publication date: July 22, 2010Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Wei-Tsung Huang, Pi-Kuang Chuang, Shih-Ming Chen, Hsiao-Ying Yang
-
Publication number: 20090236665Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.Type: ApplicationFiled: July 22, 2008Publication date: September 24, 2009Applicant: VANGUARD INTERNATIONAL SEMICONDUCTORInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
-
Publication number: 20090236681Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.Type: ApplicationFiled: July 22, 2008Publication date: September 24, 2009Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang