Patents by Inventor PI-LAN CHANG
PI-LAN CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10991649Abstract: A semiconductor device includes a first substrate, a pad array, a conductive bump, a first via and a dielectric. The pad array, formed on a surface of the first substrate, includes a first type pad and a second type pad at a same level. The conductive bump connects one of the first type pad of the second type pad to a second substrate. The first via, connected to a conductive feature at a different level to the first type pad, is located within a projection area of the first type pad and directly contacts the first type pad. The second type pad is laterally connected with a conductive trace on the same level. The conductive trace is connected to a second via at a same level with the first via. The dielectric in the first substrate contacts the second type pad. The second type pad is floated on the dielectric.Type: GrantFiled: December 17, 2019Date of Patent: April 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Chao-Wen Shih, Hung-Yi Kuo, Pi-Lan Chang
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Publication number: 20200118916Abstract: A semiconductor device includes a first substrate, a pad array, a conductive bump, a first via and a dielectric. The pad array, formed on a surface of the first substrate, includes a first type pad and a second type pad at a same level. The conductive bump connects one of the first type pad of the second type pad to a second substrate. The first via, connected to a conductive feature at a different level to the first type pad, is located within a projection area of the first type pad and directly contacts the first type pad. The second type pad is laterally connected with a conductive trace on the same level. The conductive trace is connected to a second via at a same level with the first via. The dielectric in the first substrate contacts the second type pad. The second type pad is floated on the dielectric.Type: ApplicationFiled: December 17, 2019Publication date: April 16, 2020Inventors: TSUNG-YUAN YU, HAO-YI TSAI, CHAO-WEN SHIH, HUNG-YI KUO, PI-LAN CHANG
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Patent number: 10535593Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.Type: GrantFiled: April 29, 2019Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pi-Lan Chang, Chen-Shien Chen, Chin-Yu Ku, Hsu-Hsien Chen, Wei-Chih Huang, Chun-Ying Lin, Li-Chieh Chou
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Patent number: 10510652Abstract: A method of manufacturing a semiconductor device includes: receiving a first substrate with a surface; receiving a second substrate; determining a pad array on the surface of the first substrate, wherein the pad array includes a first type pad and a second type pad; forming a via pattern underlying the pad array in the first substrate according to the location of each via, wherein the first type pad in the pad array is directly contacting a via of the via pattern and the second type pad in the pad array is clear of any via of the via pattern; laterally connecting the second type pad with a conductive trace, wherein the conductive trace connects to another via that is same level with the via contacting the first type pad; and disposing a first conductive bump and a second conductive bump between the first substrate and the second substrate.Type: GrantFiled: August 15, 2016Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Chao-Wen Shih, Hung-Yi Kuo, Pi-Lan Chang
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Publication number: 20190252304Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pi-Lan Chang, Chen-Shien Chen, Chin-Yu Ku, Hsu-Hsien Chen, Wei-Chih Huang, Chun-Ying Lin, Li-Chieh Chou
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Patent number: 10276481Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.Type: GrantFiled: October 31, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pi-Lan Chang, Chen-Shien Chen, Chin-Yu Ku, Hsu-Hsien Chen, Wei-Chih Huang, Chun-Ying Lin, Li-Chieh Chou
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Publication number: 20180374785Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.Type: ApplicationFiled: October 31, 2017Publication date: December 27, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pi-Lan Chang, Chen-Shien Chen, Chin-Yu Ku, Hsu-Hsien Chen, Wei-Chih Huang, Chun-Ying Lin, Li-Chieh Chou
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Publication number: 20180047664Abstract: A method of manufacturing a semiconductor device includes: receiving a first substrate with a surface; receiving a second substrate; determining a pad array on the surface of the first substrate, wherein the pad array includes a first type pad and a second type pad; forming a via pattern underlying the pad array in the first substrate according to the location of each via, wherein the first type pad in the pad array is directly contacting a via of the via pattern and the second type pad in the pad array is clear of any via of the via pattern; laterally connecting the second type pad with a conductive trace, wherein the conductive trace connects to another via that is same level with the via contacting the first type pad; and disposing a first conductive bump and a second conductive bump between the first substrate and the second substrate.Type: ApplicationFiled: August 15, 2016Publication date: February 15, 2018Inventors: TSUNG-YUAN YU, HAO-YI TSAI, CHAO-WEN SHIH, HUNG-YI KUO, PI-LAN CHANG
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Patent number: 9437490Abstract: A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first type pad and a second type pad located on a same level. The semiconductor device further includes a conductive bump connecting either the first type pad or the second type pad to a second substrate and a via connected a conductive feature at a different level to the first type pad and the via located within a projection area of the first type pad and directly contacting the first type pad. The semiconductor device also has a dielectric in the substrate and directly contacting the second type pad, wherein the second type pad is floated on the dielectric.Type: GrantFiled: March 31, 2014Date of Patent: September 6, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Chao-Wen Shih, Hung-Yi Kuo, Pi-Lan Chang
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Publication number: 20150137355Abstract: A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first type pad and a second type pad located on a same level. The semiconductor device further includes a conductive bump connecting either the first type pad or the second type pad to a second substrate and a via connected a conductive feature at a different level to the first type pad and the via located within a projection area of the first type pad and directly contacting the first type pad. The semiconductor device also has a dielectric in the substrate and directly contacting the second type pad, wherein the second type pad is floated on the dielectric.Type: ApplicationFiled: March 31, 2014Publication date: May 21, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: TSUNG-YUAN YU, HAO-YI TSAI, CHAO-WEN SHIH, HUNG-YI KUO, PI-LAN CHANG