Abstract: A method for increasing salicide thickness and effective polysilicon width at a narrow polysilicon line while reducing resistance and reducing source/drain bridging risk in the fabrication of a silicided polysilicon gate is described. A polysilicon layer is provided overlying a gate oxide layer on a semiconductor substrate. A dielectric layer, such as silicon oxide, is deposited overlying the polysilicon layer. The silicon oxide layer, polysilicon layer, and gate oxide layer are patterned to form a polysilicon gate electrode having a silicon oxide layer on top of the gate electrode. Dielectric spacers, such as silicon nitride, are formed on the sidewalls of the gate electrode and the silicon oxide layer. In an alternative, silicon spacers may be formed between the gate and the silicon nitride spacers to increase the effective width of the polysilicon line. Source and drain regions associated with the gate electrode are formed within the semiconductor substrate.

Abstract: A method for increasing salicide thickness and effective polysilicon width at a narrow polysilicon line while reducing resistance and reducing source/drain bridging risk in the fabrication of a silicided polysilicon gate is described. A polysilicon layer is provided overlying a gate oxide layer on a semiconductor substrate. A dielectric layer, such as silicon oxide, is deposited overlying the polysilicon layer. The silicon oxide layer, polysilicon layer, and gate oxide layer are patterned to form a polysilicon gate electrode having a silicon oxide layer on top of the gate electrode. Dielectric spacers, such as silicon nitride, are formed on the sidewalls of the gate electrode and the silicon oxide layer. In an alternative, silicon spacers may be formed between the gate and the silicon nitride spacers to increase the effective width of the polysilicon line. Source and drain regions associated with the gate electrode are formed within the semiconductor substrate.