Patents by Inventor Piebe A. Zijlstra

Piebe A. Zijlstra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7932560
    Abstract: A method of forming a substrate contact in a semiconductor device, comprising the steps of providing a semiconductor base substrate (2) having a buried oxide (BOX) layer (4) and a thin active semiconductor layer (103) on the BOX layer (4), forming a trench (104) in the active semiconductor layer (103) and the Box layer (4) to the semiconductor base substrate (2) below, and then depositing another active semiconductor (epitoxial) layer (6) over the remaining active semiconductor layer (103) and in the trench (104) to create the substrate contact. The trench (104) is etched at a location on the wafer corresponding to a scribe lane (106).
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: April 26, 2011
    Assignee: NXP B.V.
    Inventor: Piebe A. Zijlstra
  • Publication number: 20100163993
    Abstract: A method of forming a substrate contact in a semiconductor device, comprising the steps of providing a semiconductor base substrate (2) having a buried oxide (BOX) layer (4) and a thin active semiconductor layer (103) on the BOX layer (4), forming a trench (104) in the active semiconductor layer (103) and the Box layer (4) to the semiconductor base substrate (2) below, and then depositing another active semiconductor (epitoxial) layer (6) over the remaining active semiconductor layer (103) and in the trench (104) to create the substrate contact. The trench (104) is etched at a location on the wafer corresponding to a scribe lane (106).
    Type: Application
    Filed: January 10, 2007
    Publication date: July 1, 2010
    Applicant: NXP B.V.
    Inventor: Piebe A. Zijlstra
  • Patent number: 5425842
    Abstract: A method of manufacturing a semiconductor device includes the step of providing a reaction chamber (3) in which a layer of material (2) is deposited on a semiconductor slice (1) which is placed on a support (4) in the reaction chamber, a process gas being conducted towards the slice (1) through a gas inlet system (6) which is provided with a perforated gas inlet plate (9) arranged opposite the support (4). The reaction chamber is, between depositions, periodically cleaned through generation of a plasma between the support (4) and the gas inlet plate (9) in a gas mixture comprising fluorine or a fluorine compound and oxygen or an oxygen compound. A portion of the gas mixture which is comparatively rich in oxygen is conducted into the reaction chamber through the gas inlet system (6) with the gas inlet plate (9), while a portion of the gas mixture comparatively poor in oxygen is conducted into the reaction chamber through an auxiliary inlet system (23).
    Type: Grant
    Filed: June 8, 1993
    Date of Patent: June 20, 1995
    Assignee: U.S. Philips Corporation
    Inventor: Piebe A. Zijlstra