Abstract: A method of increasing enterprise alliance or successful cooperation comprising collecting the basic information and the news information of several target units. According to the above basic information, the target units are classified into several classifications. An assessment is performed based on the above news information and the basic information, thereby generating several items and the item points. The corresponding classifications, the items and the items points of above target unit are stored. A plurality of electronic mails is transmitted to a portion of the target units depending on the above classifications, items and above items points. Therefore, some common consensuses are obtained or some titles are prepared from the specific contents of the electronic mails returned by the targeted partners.

Abstract: A semiconductor market development and resource management method compriseing collecting at least one client's data regarding a semiconductor industry. The data is collected and a client management database is established. The collected data in the client management database cooperates with at least one assessment condition to analyze and convert the data into knowledge capable of supporting the enterprise management.

Abstract: A NAND or NOR content-addressable memory (CAM) cell, which selectively use single port, tow ports, or three ports for operations depending on design requirements. Only n-channel transistors or p-channel transistors design these NAND or NOR CAM cells. In such designs, one-port bit line with one-port word line, or one-port bit line with two-port word lines, or two-port bit lines with two-port word lines are provided for meeting different operations and pruposes.

Abstract: A 2-port memory device is provided. The 2-port memory device is necessary to be periodically refreshed to maintain the data stored in cells of the memory device. The memory device can be accessed by read/write operation and a refresh operation without any interference with each other. Such device can provide a very high speed accessing and the operating frequency of the memory device can be easily increased significantly.

Abstract: An operation method for a static random access memory (SRAM) device. The SRAM device has a plurality of memory cells. Each of the memory cells is periodically refreshed to retain valid data. The operation method comprising receiving an access address and a refresh address for the SRAM device and detecting whether a transition pulse and a refresh pulse being generated. The access address is used for accessing data stored in the SRAM device and the refresh address is used for periodically refreshing the memory cell in the SRAM. The transition pulse is generated by an address transition detector when a read/write operation is issued. The refresh pulse is generated in response to a refresh clock being in an active state.

Abstract: An apparatus and an operation method of a content addressable memory (CAM). The content addressable memory has a memory array and a frequency multiplier. The memory array has a memory cell row, which has a plurality of memory portions and a tag-compare portion. Each memory portion is used to store bit data. The tag-compare portion receives a compare data signal, which is compared to the bit data stored in all the memory portions. The memory portions are connected to the tag-compare portion in parallel. The frequency multiplier receives an external drive signal, and outputs an internal compare signal after multiplying a frequency of the drive signal with a certain numeric. The tag-compare portion sequentially compares the compare data signal with the bit data stored in each memory portion according to the clock of the internal compare signal, and outputs a match signal.

Abstract: A NAND or NOR content-addressable memory (CAM) cell, which selectively use single port, tow ports, or three ports for operations depending on design requirements. Only n-channel transistors or p-channel transistors design these NAND or NOR CAM cells. In such designs, one-port bit line with one-port word line, or one-port bit line with two-port word lines, or two-port bit lines with two-port word lines are provided for meeting different operations and pruposes.

Abstract: A DRAM module and a method of replacing a damaged DRAM cell in the DRAM module with a SRAM. The DRAM module has at least a non-volatile memory and a DRAM control logic circuit. In the process of replacing the damaged DRAM with the SRAM, the damaged address data is compared to DRAM address data. If the data are consistent, the address of the SRAM is used to access data. Meanwhile, the output enabling signal of the DRAM cell is turned off. It can thus assist the computer to correctly find the good DRAM cell for data access, so as to ensure a normal operation of the computer.

Abstract: A 2-port memory device is provided. The 2-port memory device is necessary to be periodically refreshed to maintain the data stored in cells of the memory device. The memory device can be accessed by read/write operation and a refresh operation without any interference with each other. Such device can provide a very high speed accessing and the operating frequency of the memory device can be easily increased significantly.

Abstract: A DRAM module and a method of replacing a damaged DRAM cell in the DRAM module with a SRAM. The DRAM module has at least a non-volatile memory and a DRAM control logic circuit. In the process of replacing the damaged DRAM with the SRAM, the damaged address data is compared to DRAM address data. If the data are consistent, the address of the SRAM is used to access data. Meanwhile, the output enabling signal of the DRAM cell is turned off. It can thus assist the computer to correctly find the good DRAM cell for data access, so as to ensure a normal operation of the computer.

Abstract: An operation method for a static random access memory (SRAM) device. The SRAM device has a plurality of memory cells. Each of the memory cells is periodically refreshed to retain valid data. The operation method comprising receiving an access address and a refresh address for the SRAM device and detecting whether a transition pulse and a refresh pulse being generated. The access address is used for accessing data stored in the SRAM device and the refresh address is used for periodically refreshing the memory cell in the SRAM. The transition pulse is generated by an address transition detector when a read/write operation is issued. The refresh pulse is generated in response to a refresh clock being in an active state.

Abstract: An apparatus and an operation method of a content addressable memory (CAM). The content addressable memory has a memory array and a frequency multiplier. The memory array has a memory cell row, which has a plurality of memory portions and a tag-compare portion. Each memory portion is used to store bit data. The tag-compare portion receives a compare data signal, which is compared to the bit data stored in all the memory portions. The memory portions are connected to the tag-compare portion in parallel. The frequency multiplier receives an external drive signal, and outputs an internal compare signal after multiplying a frequency of the drive signal with a certain numeric. The tag-compare portion sequentially compares the compare data signal with the bit data stored in each memory portion according to the clock of the internal compare signal, and outputs a match signal.

Abstract: A decode circuit provides timing and control signals to a DRAM to insure a minimum current surge during activation of bit-lines within the DRAM during a row address strobe (RAS) cycle. Providing the minimum current surge during the RAS cycle prevents damage to a battery attached to a DRAM when the bit-lines of the DRAM are activated, while minimizing the time to access digital data retain within the DRAM array. The decode circuit within a DRAM will receive a digital address word indicating column locations of a plurality of desired digital data bits retained within an array of DRAM memory cells, decode digital address word, and selectively activate bit-lines of said column locations of said plurality of desired digital data bits at a first time and activate all remaining bit-lines at times subsequent to the first time to minimize RAS cycle current. The decode circuit has a decode logic circuit to select one of the column locations that is designated by the digital address date word.

Abstract: A method is provided for performing a BIST (built-in self test) procedure on embedded memory through a time-division multipexed scheme with a reduced number of probing pads. This method is characterized in the use of a time-division multipexed scheme to obtain the addresses of bad memory cells so that these address data can be used to indicate the locations of the bad memory cells during repair process. Moreover, this method is characterized in that it requires only a fewer number of probing pads than the prior art so that the required layout area for the BIST procedure can be reduced as compared to the prior art. This method is therefore more cost-effective to implement than the prior art.

Abstract: A DRAM module and a method of replacing a damaged DRAM cell in the DRAM module with a SRAM. The DRAM module has at least a non-volatile memory and a DRAM control logic circuit. In the process of replacing the damaged DRAM with the SRAM, the damaged address data is compared to DRAM address data. If the data are consistent, the address of the SRAM is used to access data. Meanwhile, the output enabling signal of the DRAM cell is turned off. It can thus assist the computer to correctly find the good DRAM cell for data access, so as to ensure a normal operation of the computer.

Abstract: The present invention provides a memory refresh structure having a memory array and two clock generators. The memory array has a plurality of cells grouped into original segments. The two clock generators generate two clock signals, CLK0 and CLK1. CLK0 takes responsibility for the refresh operations of the cells in the original segments to meet an original refresh time. A portion of the original segments that having at least one cell whose retention time is longer than the original refresh time are defined as first segments. CLK1 takes responsibility for the refresh operations of the cells in the first segments to make the refreshed cell meet a first refresh time shorter than the original refresh time.

Abstract: In this invention is disclosed a method of burn-in testing either DRAM's or FeRAM's at the wafer level. A stress voltage is applied across all storage capacitors of a DRAM or a FeRAM during a wafer level burn-in test to weed out memory chips with weak memory cells. Three pads are added to the memory chips to accommodate a burn-in signal, a word line voltage and a stress voltage. The burn-in signal disables normal memory operations, powers on all word lines, and connects a stress voltage across the storage capacitors of the memory cells. The stress voltage across the storage capacitors is the difference between the externally applied stress voltage and a low voltage from the bit lines that is connected to the memory cells by means of the word lines. The wafer level burn-in provides a way to improve throughput by eliminating weak product early in the manufacturing process.

Abstract: A semiconductor integrated circuit device includes a plurality of memory cells subdivided into array blocks each including M cell rows and N cell columns. The array blocks are arranged in array block rows and array block columns. Each cell of each cell row of each array block is coupled to an associated one of M word lines. Each cell of each cell column is selectively coupled to develop a data signal transmitted between an associated bit line pair including a primary bit line and a complementary bit line. A row decoder is coupled to provide a corresponding row address signal to each of the M word lines for addressing the cell rows.

Abstract: A circuit is provided for use on a wafer formed with a plurality of dice on each of which a memory device, such as a DRAM (dynamic random access memory) device to perform a burn-in operation on the memory device so as to test the reliability thereof. By this circuit, a plurality of pads are formed in the scribe lines that are used as reference marks in the cutting apart of the dice. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the dice where each memory device is formed. The burn-in operation is more convenient, quick, and cost-effective to implement.

Abstract: A method is provided for use on a wafer formed with a plurality of dice on each of which a memory device, such as a DRAM (dynamic random access memory) device to perform a burn-in operation on the memory device so as to test the reliability thereof. By this method, a plurality of pads are formed in the scribe lines that are used as reference marks in the cutting apart of the dice. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the dice where each memory device is formed. The burn-in operation is more convenient, quick, and cost-effective to implement.