Patents by Inventor Pier E. Zani

Pier E. Zani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making electronic power device realized by a series of elementary semiconductor components connected in parallel
    Patent number: 5397745
    Abstract: Plural modular elementary semiconductor power components are respectively contained within plural semiconductor chip regions of a same semiconductor slice. A metallic layer covers a first surface of the semiconductor slice and is commonly connected to anode electrodes of the plural elementary power components. Plural space apart quadrangular metallic layer regions respectively cover the plural semiconductor chip regions on a second surface of the semiconductor slice and are respectively connected to cathode electrodes of the plural elementary power components. Plural first metallic tracks are spaced apart from and surround the respective plural metallic layer regions on the second surface of the semiconductor slice. Each respective first metallic track is connected to a control electrode of the elementary power component contained within the semiconductor chip regions surrounded by the respective first metallic track.
    Type: Grant
    Filed: June 17, 1993
    Date of Patent: March 14, 1995
    Assignees: SGS-Thomson Microelectronics S.r.L., Ansaldo Trasporti S.p.A.
    Inventors: Giuseppe Ferla, Cesare Ronsisvalle, Pier E. Zani
  • Electronic power device having plural elementary semiconductor components connected in parallel
    Patent number: 5250821
    Abstract: Plural modular elementary semiconductor power components are respectively contained within plural semiconductor chip regions of a same semiconductor slice. A metallic layer covers a first surface of the semiconductor slice and is commonly connected to anode electrodes of the plural elementary power components. Plural space apart quadrangular metallic layer regions respectively cover the plural semiconductor chip regions on a second surface of the semiconductor slice and are respectively connected to cathode electrodes of the plural elementary power components. Plural first metallic tracks are spaced apart from and surround the respective plural metallic layer regions on the second surface of the semiconductor slice. Each respective first metallic track is connected to a control electrode of the elementary power component contained within the semiconductor chip regions surrounded by the respective first metallic track.
    Type: Grant
    Filed: January 9, 1992
    Date of Patent: October 5, 1993
    Assignees: SGS-Thomson Microelectronisc S.r.L., Ansaldo Transporti S.p.A.
    Inventors: Giuseppe Ferla, Cesare Ronsisvalle, Pier E. Zani