Patents by Inventor Pier Francese
Pier Francese has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10320332Abstract: Octagonal phase rotator includes an I-mixer having an I-DAC for steering current between positive and negative phases of an in-phase signal depending on k I-DAC control bits of a control code, a Q-mixer having a Q-DAC for steering current between the positive/negative phases of a quadrature signal depending on k Q-DAC control bits of the code, and an IQ-mixer having n IQ-mixer units each comprising an IQ-DAC for switching a second current unit between the in-phase and quadrature signals, in dependence on a respective bit of n IQ-DAC control bits, and between the positive/negative phases of the in-phase and quadrature signals via I and Q polarity switches respectively of that component. I and Q polarity switches of some different IQ-DAC components switch depending on different I-DAC control bits and Q-DAC control bits respectively. A summation circuit sums weighted output signals from the mixers to produce an output signal of phase.Type: GrantFiled: November 10, 2017Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventor: Pier A. Francese
-
Publication number: 20180262161Abstract: Octagonal phase rotator includes an I-mixer having an I-DAC for steering current between positive and negative phases of an in-phase signal depending on k I-DAC control bits of a control code, a Q-mixer having a Q-DAC for steering current between the positive/negative phases of a quadrature signal depending on k Q-DAC control bits of the code, and an IQ-mixer having n IQ-mixer units each comprising an IQ-DAC for switching a second current unit between the in-phase and quadrature signals, in dependence on a respective bit of n IQ-DAC control bits, and between the positive/negative phases of the in-phase and quadrature signals via I and Q polarity switches respectively of that component. I and Q polarity switches of some different IQ-DAC components switch depending on different I-DAC control bits and Q-DAC control bits respectively. A summation circuit sums weighted output signals from the mixers to produce an output signal of phase.Type: ApplicationFiled: November 10, 2017Publication date: September 13, 2018Inventor: Pier A. Francese
-
Patent number: 10038468Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: GrantFiled: August 8, 2017Date of Patent: July 31, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pier A. Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
-
Patent number: 9991848Abstract: Octagonal phase rotator includes an I-mixer having an I-DAC for steering current between positive and negative phases of an in-phase signal depending on k I-DAC control bits of a control code, a Q-mixer having a Q-DAC for steering current between the positive/negative phases of a quadrature signal depending on k Q-DAC control bits of the code, and an IQ-mixer having n IQ-mixer units each comprising an IQ-DAC for switching a second current unit between the in-phase and quadrature signals, in dependence on a respective bit of n IQ-DAC control bits, and between the positive/negative phases of the in-phase and quadrature signals via I and Q polarity switches respectively of that component. I and Q polarity switches of some different IQ-DAC components switch depending on different I-DAC control bits and Q-DAC control bits respectively. A summation circuit sums weighted output signals from the mixers to produce an output signal of phase.Type: GrantFiled: March 7, 2017Date of Patent: June 5, 2018Assignee: International Business Machines CorporationInventor: Pier A. Francese
-
Patent number: 9860087Abstract: Embodiments of the present invention may provide the capability for reducing power consumption in a speculative decision feedback equalizer by powering up the speculative path that is going to take the next decision based on the previous decision, and holding other paths in a reset low-power condition. For example, a Speculative Decision Feedback Equalizer may comprise a plurality of speculative paths, circuitry to provide power to a speculative path that will take the next decision based on the current decision, and circuitry to keep at least one other speculative path in a reset state with low or reduced power consumption.Type: GrantFiled: August 31, 2016Date of Patent: January 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pier A. Francese, Elisa Sacco
-
Publication number: 20170331510Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: ApplicationFiled: August 8, 2017Publication date: November 16, 2017Inventors: Pier A. Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
-
Patent number: 9748927Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: GrantFiled: September 8, 2016Date of Patent: August 29, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pier A. Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
-
Publication number: 20170040975Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: ApplicationFiled: September 8, 2016Publication date: February 9, 2017Inventors: Pier A. Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
-
Patent number: 9509281Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: GrantFiled: March 28, 2016Date of Patent: November 29, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pier A. Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
-
Patent number: 9258109Abstract: The invention relates to a phase rotation method for a clock recovery, comprising the steps of: providing a timing estimation value that indicates for each input data symbol at least whether an input data sample has been sampled early or late by a sampling clock signal; generating a phase offset value indicating a phase rotation of the sampling clock signal based on the timing estimation value; modifying the timing function value based on a change of the phase offset value, resulting in the timing estimation value.Type: GrantFiled: December 5, 2014Date of Patent: February 9, 2016Assignee: International Business Machines CorporationInventors: Pier A. Francese, Lukas Kull, Thomas H. Toifl
-
Publication number: 20150180648Abstract: The invention relates to a phase rotation method for a clock recovery, comprising the steps of: providing a timing estimation value that indicates for each input data symbol at least whether an input data sample has been sampled early or late by a sampling clock signal; generating a phase offset value indicating a phase rotation of the sampling clock signal based on the timing estimation value; modifying the timing function value based on a change of the phase offset value, resulting in the timing estimation value.Type: ApplicationFiled: December 5, 2014Publication date: June 25, 2015Inventors: Pier A. Francese, Lukas Kull, Thomas H. Toifl
-
Patent number: 8917762Abstract: A decision feedback equalizer (DFE) slice for a receiver includes a plurality of non-speculative DFE taps; and 3 speculative DFE taps, wherein the 3 speculative DFE taps comprise first and second multiplexer stages, each of the first and second multiplexer stages including 4 comparator latches, each of the 4 comparator latches having a programmable offset; and a multiplexer that receives 4 comparator latch outputs from the 4 comparator latches and outputs a multiplexer stage output, wherein the multiplexer is controlled by previous symbol decisions dn-2 and dn-3; and wherein the 3 speculative taps further comprise a 2:1 decision multiplexer stage that receives the multiplexer stage outputs of the first and second multiplexer stages and is controlled by a previous symbol decision dn-1 to output a slice output signal dn.Type: GrantFiled: June 1, 2012Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Pier A. Francese, Christian I. Menolfi, Thomas H. Toifl
-
Publication number: 20130322512Abstract: A decision feedback equalizer (DFE) slice for a receiver includes a plurality of non-speculative DFE taps; and 3 speculative DFE taps, wherein the 3 speculative DFE taps comprise first and second multiplexer stages, each of the first and second multiplexer stages including 4 comparator latches, each of the 4 comparator latches having a programmable offset; and a multiplexer that receives 4 comparator latch outputs from the 4 comparator latches and outputs a multiplexer stage output, wherein the multiplexer is controlled by previous symbol decisions dn-2 and dn-3; and wherein the 3 speculative taps further comprise a 2:1 decision multiplexer stage that receives the multiplexer stage outputs of the first and second multiplexer stages and is controlled by a previous symbol decision dn-1 to output a slice output signal dn.Type: ApplicationFiled: June 1, 2012Publication date: December 5, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pier A. Francese, Christian I. Menolfi, Thomas H. Toifl
-
Patent number: 7948423Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.Type: GrantFiled: April 15, 2010Date of Patent: May 24, 2011Assignee: National Semiconductor CorporationInventors: Robert Callaghan Taft, Heinz Werker, Pier Francese, David Brian Barkin
-
Publication number: 20100201559Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.Type: ApplicationFiled: April 15, 2010Publication date: August 12, 2010Inventors: Robert Callaghan Taft, Heinz Werker, Pier Francese, David Brian Barkin
-
Patent number: 7728753Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.Type: GrantFiled: October 13, 2008Date of Patent: June 1, 2010Assignee: National Semiconductor CorporationInventors: Robert Callaghan Taft, Heinz Werker, Pier Francese, David Barkin
-
Publication number: 20100090876Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.Type: ApplicationFiled: October 13, 2008Publication date: April 15, 2010Applicant: National Semiconductor CorporationInventors: Robert Callaghan Taft, Heinz Werker, Pier Francese, David Brian Barkin