Abstract: Methods and example implementations described herein are generally directed to a System on Chip (SoC) design and verification system and method that constructs SoC from functional building blocks circuits while concurrently taking into account numerous chip level design aspects along with the generation of a simulation environment for design verification. An aspect of the present disclosure relates to a method for generating a System on Chip (SoC) from a floor plan having one or more integration descriptions. The method includes the steps of generating one or more connections between the integration descriptions of the floor plan based at least on a traffic specification, and conducting a design check process on the floor plan. If the design check process on the floor plan is indicative of passing the design check process, then the method generates the SoC according to the one or more connections generated between the integration descriptions.

Abstract: Methods and example implementations described herein are generally directed to repository of integration description of hardware intellectual property (IP) for NoC construction and SoC integration. An aspect of the present disclosure relates to a method for managing a repository of hardware intellectual property (IP) for Network-on-Chip (NoC)/System-on-Chip (SoC) construction. The method includes the steps of storing one or more integration descriptions of the hardware IP in the repository, selecting at least one integration description as a parsed selection from said one or more integration descriptions of the hardware IP for incorporation in the NoC/SoC, and generating the NoC/SoC at least from the parsed selection.

Abstract: A system and method for automatic crossbar generation and router connections for Network-on-Chip (NoC) topology generation is disclosed. Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating topology for a given SoC by significantly improving system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, along with indicating system level routes to be taken for traffic flows using the NoC interconnect architecture. Aspects of the present disclosure further relate to determining optimal positions of ports within hosts so as to enable low latency and higher message transmission efficiency between the hosts. In yet another aspect, a computationally efficient NoC topology is generated based on allocation of routers and NoC channels so as to identify most efficient routes for various system flows between hosts.

Abstract: Methods, systems, and non-transitory computer readable medium for automatically characterizing performance of a System-on-Chip (SoC) and/or Network-on-Chip (NoC) with respect to latency and throughput attributes of one or more traffic flows/profiles under varying traffic load conditions. The characterization of performance may involve a plot representative of latency and throughput, depending on the desired implementation.

Abstract: Methods and example implementations described herein are generally directed to a System on Chip (SoC) design and verification system and method that constructs SoC from functional building blocks circuits while concurrently taking into account numerous chip level design aspects along with the generation of a simulation environment for design verification. An aspect of the present disclosure relates to a method for generating a System on Chip (SoC) from a floor plan having one or more integration descriptions. The method includes the steps of generating one or more connections between the integration descriptions of the floor plan based at least on a traffic specification, and conducting a design check process on the floor plan. If the design check process on the floor plan is indicative of passing the design check process, then the method generates the SoC according to the one or more connections generated between the integration descriptions.

Abstract: A system and method for automatic crossbar generation and router connections for Network-on-Chip (NoC) topology generation is disclosed. Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating topology for a given SoC by significantly improving system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, along with indicating system level routes to be taken for traffic flows using the NoC interconnect architecture. Aspects of the present disclosure further relate to determining optimal positions of ports within hosts so as to enable low latency and higher message transmission efficiency between the hosts. In yet another aspect, a computationally efficient NoC topology is generated based on allocation of routers and NoC channels so as to identify most efficient routes for various system flows between hosts.

Abstract: Methods and example implementations described herein are generally directed to repository of integration description of hardware intellectual property (IP) for NoC construction and SoC integration. An aspect of the present disclosure relates to a method for managing a repository of hardware intellectual property (IP) for Network-on-Chip (NoC)/System-on-Chip (SoC) construction. The method includes the steps of storing one or more integration descriptions of the hardware IP in the repository, selecting at least one integration description as a parsed selection from said one or more integration descriptions of the hardware IP for incorporation in the NoC/SoC, and generating the NoC/SoC at least from the parsed selection.

Abstract: The present disclosure is directed to system-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology. The present disclosure enables transformation from physical placement to logical placement to satisfy bandwidth requirements while maintaining lowest area and lowest routing with minimum cost (wiring and buffering) and latency. In an aspect, method according to the present application includes the steps of receiving at least a floor plan description of an System-on-Chips (SoCs), transforming said floor plan description into at least one logical grid layout of one or more rows and one or more columns, optimizing a number of said one or more rows and said one or more columns based at least on any or combination of a power, an area, or a performance to obtain an optimized transformed logical grid layout, and generating said Network-on-Chip (NoC) topology at least from said optimized transformed logical grid layout.

Abstract: In example implementations, the specification is processed to determine the characteristics of the NoC to be generated, the characteristics of the flow (e.g. number of hops, bandwidth requirements, type of flow such as request/response, etc.), flow mapping decision strategy (e.g., limit on number of new virtual channels to be constructed, using of existing VCs, yx/xy mapping), and desired strategy to be used for how the flows are to be mapped to the network. In such processing, the machine learning algorithm can provide a determination as to if a flow is acceptable or not in view of the specification (e.g., via a Q score). In example implementations, the machine learning decisions can be applied on a flow by flow basis, and can involve supervised learning and unsupervised learning algorithms.

Abstract: Example implementations described herein are directed to systems and methods for generating a Network on Chip (NoC), which can involve determining a plurality of traffic flows from a NoC specification; grouping the plurality of traffic flows into a plurality of groups; utilizing a first machine learning algorithm to determine a sorting order on each of the plurality of groups of traffic flows; generating a list of traffic flows for NoC construction from the plurality of groups of traffic flows based on the sorting order; utilizing a second machine learning algorithm to select one or more mapping algorithms for each group of the plurality of groups of traffic flows for NoC construction; and generating the NoC based on a mapping from the selection of the one or more mapping algorithms.

Abstract: In an aspect, the present disclosure provides a method that comprises automatic generation of a NoC from specified topological information based on projecting NoC elements of the NoC onto a grid layout. In an aspect, the specified topological information, including specification of putting constraints on positions/locations of NoC elements and links thereof, can be input by a user in real space, and can then be projected on the grid layout.

Abstract: In an aspect, the present disclosure provides a method that comprises automatic generation of a NoC from specified topological information based on projecting NoC elements of the NoC onto a grid layout. In an aspect, the specified topological information, including specification of putting constraints on positions/locations of NoC elements and links thereof, can be input by a user in real space, and can then be projected on the grid layout.

Abstract: The present disclosure is directed to extracting features from a NoC for machine learning construction. Example implementations include a method for generating a Network on Chip (NoC), wherein the method can extract at least one feature from a NoC specification to derive at least one of: grid features, traffic features and topological features associated with the NoC. The method can perform a process on the at least one of the grid features, the traffic features and the topological features associated with the NoC to determine at least one of an evaluation of at least one mapping strategy selected from a plurality of mapping strategies of the NoC based on a quality metric, and the selection of the at least one mapping strategy is based on the quality metric. The method can further perform generate the NoC based on the process.

Abstract: In an aspect, the present disclosure provides a method that comprises automatic generation of a NoC from specified topological information based on projecting NoC elements of the NoC onto a grid layout. In an aspect, the specified topological information, including specification of putting constraints on positions/locations of NoC elements and links thereof, can be input by a user in real space, and can then be projected on the grid layout.

Abstract: The present disclosure is directed to system-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology. The present disclosure enables transformation from physical placement to logical placement to satisfy bandwidth requirements while maintaining lowest area and lowest routing with minimum cost (wiring and buffering) and latency. In an aspect, method according to the present application includes the steps of receiving at least a floor plan description of an System-on-Chips (SoCs), transforming said floor plan description into at least one logical grid layout of one or more rows and one or more columns, optimizing a number of said one or more rows and said one or more columns based at least on any or combination of a power, an area, or a performance to obtain an optimized transformed logical grid layout, and generating said Network-on-Chip (NoC) topology at least from said optimized transformed logical grid layout.

Abstract: Example implementations described herein are directed to systems and methods for generating a Network on Chip (NoC), which can involve determining a plurality of traffic flows from a NoC specification; grouping the plurality of traffic flows into a plurality of groups; utilizing a first machine learning algorithm to determine a sorting order on each of the plurality of groups of traffic flows; generating a list of traffic flows for NoC construction from the plurality of groups of traffic flows based on the sorting order; utilizing a second machine learning algorithm to select one or more mapping algorithms for each group of the plurality of groups of traffic flows for NoC construction; and generating the NoC based on a mapping from the selection of the one or more mapping algorithms.

Abstract: Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating/constructing NoC based on one or more strategies that are selected by a machine-learning engine (MLE) from a plurality of available strategies based on an input NoC specification. In an aspect, the method can include the steps of processing a Network on Chip (NoC) specification through a process to generate a vector for a plurality of NoC generation strategies, wherein the vector is indicative of which strategies from the plurality of NoC generation strategies are to be used to generate the NoC to meet a quality metric; and generating the NoC by using the strategies from the plurality of NoC generation strategies indicated by the vector as the strategies to be used to generate the NoC, wherein the process is generated through a machine learning process that is trained for the plurality of NoC generation strategies.

Abstract: The present disclosure is directed to machine learning (ML) based network-on-chip (NoC) construction. Example implementations of the present disclosure utilize a ML process for making decisions to evaluate whether a NoC design finally obtained is optimized for a desired implementation during construction of a NoC. The ML process for the construction of the NoC maximizes entropy for one or more features of the NoC. In an example implementation, the present disclosure provides a ML predictor that receives inputs in the form of features that are extracted from a specification, a plurality of mapping strategies, and quality metrics obtained by implementing a mapping strategy on the NoC to generate an output that provide an indication as to whether the set of strategies results in a good or bad design or whether the provided strategy meets a threshold for the quality metric.

Abstract: The present disclosure is directed to extracting features from a NoC for machine learning construction. Example implementations include a method for generating a Network on Chip (NoC), wherein the method can extract at least one feature from a NoC specification to derive at least one of: grid features, traffic features and topological features associated with the NoC. The method can perform a process on the at least one of the grid features, the traffic features and the topological features associated with the NoC to determine at least one of an evaluation of at least one mapping strategy selected from a plurality of mapping strategies of the NoC based on a quality metric, and the selection of the at least one mapping strategy is based on the quality metric. The method can further perform generate the NoC based on the process.

Abstract: The present disclosure is directed to machine learning (ML) based network-on-chip (NoC) construction. Methods, systems, and computer readable mediums of the present disclosure utilize a ML process for making decisions to evaluate whether a NoC design finally obtained is actually the most optimal and efficient one or not during construction of a NoC. ML process for the construction of the NoC maximizes entropy for one or more features of the NoC. In an example implementation, the present disclosure provides a machine learning algorithm/predictor that receives inputs in the form of features that are extracted from a specification, a plurality of mapping strategies, a quality metrics) obtained by implementing a mapping strategy on the NoC, and one or more performance function (user requirement) to generate an output showing whether the selected strategy for the construction of the NoC yields a good result or a bad result based on learning/training.