Abstract: An integrated EPROM device which can be manufactured using standard high-definition photolithographic techniques with unit cells of markedly reduced dimensions as compared to the minimum dimensions that can be achieved with the prior art, has field isolation structures between adjacent cells along rows of the array in the form of continuous isolation strips which extend for the whole column length of the array, thus avoiding the problems associated with photolithographic defining rectangular geometries. The electrical interconnection between the sources of the cells of each row is achieved by a special metal source "line" formed between two adjacent gate lines, using for the purpose a conformally deposited metal layer from which both the drain contacts and these source interconnection metal "lines" are created in a self-alignment way.

Abstract: Process for the manufacture of calibration structures particularly for the calibration of machines for measuring alignment in integrated circuits in general, the peculiarity of which consists in the fact that calibration structures are provided in which the alignment of one layer with respect to another layer is set to a known extent by means of a single masking.

Abstract: A cell array for EPROM or ROM type memories has drain and source interconnection metal lines connecting in common drain and source regions, respectively, of the cells arranged on a same row of the array formed directly on the semiconductor substrate, superimposed at crossings to uninterrupted isolation strips formed on the semiconductor substrate for separating cells belonging to two adjacent columns of the array, and gate interconnection lines (WORD LINES), connecting the control gate electrodes of cells arranged on a same column, which run parallel to and between said isolation strips and superimposed at crossings to said underlying source and drain lines (BIT LINES). The array is markedly more compact than an array made according to the prior art though utilizing fabrication apparatuses with similar optical resolution, while maximizing the source and drain contact areas of the cells.

Abstract: Step coverage in contacts may be improved by forming a tapered hole through a dielectric layer by:a) plasma (RIE) etching through a "contact" mask the dielectric for a depth shorter than the thickness of the layer leaving a residual thickness of dielectric on the bottom of the etch;b) removing the residual masking material;c) conformally depositing a TEOS layer;d) etching the conformally deposited TEOS layer without a mask in (RIE) plasma until exposing the underlying silicon or polysilicon with which the contact must be established.The anisotropic etching of the TEOS layer, conformally deposited on the partially pre-etched dielectric layer, determines a "self-aligned" exposition of the underlying silicon or polysilicon and leaves a tapered TEOS residue on the vertical pre-etched hole's walls, thus providing a desired tapering of the contact hole. Photolithographic definition is no longer a critical factor.

Abstract: An integrated EPROM device which can be manufactured using standard high definition photolithographic techniques with unit cells of markedly reduced dimensions as compared to the minimum dimensions that can be achieved with the prior art, has field isolation structures between adjacent cells along rows of the array in the form of continuous isolation strips which extend for the whole column length of the array, thus avoiding the problems associated with photolithographic defining rectangular geometries. The electrical interconnection between the sources of the cells of each row is achieved by a special metal source "line", formed between two adjacent gate lines, using for the purpose a conformally deposited metal layer from which both the drain contacts and these source interconnection metal "lines" are created in a self-alignment way.

Abstract: Encased (BOX) trench insolation structures in a silicon substrate are formed by firstly RIE etching an ONO multilayer (Oxide-Nitrite-Oxide) formed on the surface of a monocrystalline silicon substrate through a mask defining the active areas until exposing the silicon. A successive deposition of a conformable TEOS oxide layer followed by a "blanket" RIE etching, leave tapered "spacers" on the vertical etched flanks of the ONO multilayer. Through such a self-aligned "aperture" an isotropic plasma etching (round-etch) of the silicon is performed until the lateral, under-cut, etch front below the oxide spacers reaches the bottom layer of the isolation area defining etching previously conducted through the ONO multilayer. The peculiarities of the round-etch profile are thus fully exploited for more easily implanting the walls and bottom of the trench and avoiding the presence of electric field affecting sharp corners.

Abstract: A process for forming self-aligned metal-semiconductor contacts in integrated MISFET devices determining during a phase of the fabrication the presence on the surface of a wafer of parallel gate lines of polycrystalline silicon provided with lateral "spacers", is founded on the formation of a dielectric oxide layer of a differentiated thickness, having a reduced thickness on the bottom of the valley between two adjacent gate lines wherein the contacts must be formed. The method comprises conformably depositing a first layer of dielectric silicon oxide, a second layer of precursor polycrystalline silicon and a third layer of nitride, followed by depositing a layer of planarization SOG. By blanket etching the SOG layer and the nitride layer, the crests of the precursor polycrystalline silicon layer are exposed. A residual layer of nitride is left inside the valley between adjacent gate lines.

Abstract: A process for forming self-aligned metal-semiconductor contacts in a device comprising MISFET type structures essentially comprises conformably depositing a matrix metallic layer on the front of the wafer and the subsequent deposition of a planarization SOG layer. After having used a noncritical mask for defining the "length" of the selfaligned contacts to be formed, the SOG layer is etched until leaving a residue layer on the bottom of the valleys of the conformably deposited matrix metallic layer in areas between two adjacent gate lines of polysilicon. A selective etching of the matrix layer using said SOG residues as a mask, defines the contacts, self-aligned in respect to the opposite spacers of two adjacent polysilicon gate lines. An insulating dielectric layer is deposited and etched until exposing the peaks of the preformed contacts.