Abstract: An apparatus includes multiple media processing modules and a control unit. The media processing modules are configured to exchange digital media signals over a shared bus. The control unit is configured to determine a desired connectivity scheme among the media processing modules, to adaptively define, based on the desired connectivity scheme, connections that transfer the media signals among the media processing modules over the shared bus, and to instruct the media processing modules to establish the connections, by communicating with the media processing modules over a control interface that is independent of the shared bus.

Abstract: An apparatus includes multiple media processing modules and a control unit. The media processing modules are configured to exchange digital media signals over a shared bus. The control unit is configured to determine a desired connectivity scheme among the media processing modules, to adaptively define, based on the desired connectivity scheme, connections that transfer the media signals among the media processing modules over the shared bus, and to instruct the media processing modules to establish the connections, by communicating with the media processing modules over a control interface that is independent of the shared bus.

Abstract: A method for detecting signals affected by intersymbol interference provides for a path memory in the form of a trellis admitting survivor paths comprising a first and a second stage. The first stage includes a shift register exchange with a given number of states and a given length ?. The first stage outputs a first state SAkk-? on the survivor path for the best state Ak, and a second state SBkk-? on the survivor path for another state Bk. The second stage is configured as a two-state shift register exchange having a respective memory length ?, including respective first and second registers. In the respective first and second registers the survivor paths are stored leading to a respective first ?0k and second ?1k state, whereby the respective first register contains the backend of the best survivor path, while the respective second register contains the backend of an alternative survivor path.

Abstract: A method for detecting signals affected by intersymbol interference provides for a path memory being arranged in the form of a trellis admitting survivor paths comprising a first and a second stage. The first stage includes a shift register exchange with a given number of states and a given length ?. At time k-?, where ? is said given length, the first stage outputs a) a first state SAkk-? on the survivor path for the best state Ak at time k, while keeping track of the parity for the state at time k-? for each of the survivor paths in said path memory, and b) a second state SBkk-? on the survivor path for another state Bk having the same intersymbol interference state as said best state Ak and the opposite priority state. The second stage as is a two-state shift register exchange having a respective memory length ?, including respective first and second registers.

Abstract: A high-speed, wide dynamic range, digital accumulator includes a first adder stage in which an input addend is added to a value of a least significant part of an output of an accumulator from a preceding clock period. The accumulator also includes at least one second stage having incrementer/decrementer means for performing an increment, decrement or identity operation on a most significant part of the output of the accumulator. The incrementer/decrementer means includes logic means for triggering the increment, a decrement or identity operation on the most significant part of the accumulator output based on a decision made on results obtained at the previous clock period.

Abstract: A switching regulator having a switching element, a control loop for varying a duty cycle of the switching element according to a difference between a switching regulator output electric quantity and a target output electric quantity, and a digital soft start-up circuit for digitally controlling the duty cycle of the switching element, independently from said difference, in a start-up phase of the switching regulator operation.

Abstract: A transconductor includes a differential stage formed by a pair of input transistors, and a resistive line of degeneration connecting the sources of the input transistors. A bias current generator is coupled between the source of each input transistor and ground. The resistive line of degeneration is formed by one or more transistors connected in series, the gates of which are coupled to a voltage reference. The voltage reference is at least equal to the common mode voltage of the differential stage. The one or more transistors forming the resistive line of degeneration are sized to operate in the triode region.

Abstract: A method drives a three-phase motor having first, second, and third coils. The method electrically connects the first coil to a first voltage reference and the second coil to a second voltage reference while leaving the other coil floating during a first driving phase. During a second driving phase, the first coil is electrically connected to the first voltage reference and the third coil is electrically connected to the second voltage reference while the second coil is left floating. During a transition phase that immediately follows the fast driving phase and immediately precedes the second driving phase, the second coil is electrically connected alternately to the first and second voltage references. By alternately connecting the second coil to the first second voltage references and during the transition phase, the method causes the current through the second coil to reduce to zero at a slower rate than prior methods.