Patents by Inventor Pierangelo Pansana

Pierangelo Pansana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4719184
    Abstract: After growth of gate oxide, deposit and separation of a first polycrystalline silicon layer, growth of dielectric oxide and removal thereof from the transistor area, and deposit of a second polycrystalline layer, a single mask makes possible first etching of the second silicon layer and of the dielectric oxide and then of the first silicon layer of the gate oxide at the sides of the cell and transistor areas.
    Type: Grant
    Filed: March 6, 1987
    Date of Patent: January 12, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Daniele Cantarelli, Giuseppe Crisenza, Pierangelo Pansana
  • Patent number: 4488931
    Abstract: On a substrate of monocrystalline silicon there are formed, one after another, a first oxide layer, a first polycrystalline silicon layer, a second intermediate oxide layer and a second polycrystalline silicon layer which is thicker than the first. In the second polycrystalline silicon layer there is defined a structure having the desired circuit configuration. Using this polycrystalline silicon structure as a mask, the exposed parts of the intermediate oxide layer are etched until they are completely eliminated and, subsequently, an oxidation process is carried out long enough to completely convert the exposed parts of the first polycrystalline silicon layer into an oxide. Thus, from this layer is obtained a circuit structure which is self-aligned with the first structure defined in the second polycrystalline silicon layer.
    Type: Grant
    Filed: March 26, 1984
    Date of Patent: December 18, 1984
    Assignee: SGS-ATES Componenti Elettronici S.p.A.
    Inventor: Pierangelo Pansana