Abstract: A reference frequency is distributed through a packet-based network to remote elements in a system. Timing packets are periodically sent from a master timing element, to be received by at least one peripheral timing element. Echo messages are sent to the master timing element by each peripheral timing element after a unique delay, in response to the reception of a timing packet. Loopback delay measurements are included in each timing packet for each peripheral timing element. Each peripheral timing element locks a loop using only timing packets which incur a minimum loopback delay.

Abstract: A reference frequency is distributed through a packet-based network to remote elements in a system. Timing packets are periodically sent from a master timing element, to be received by at least one peripheral timing element. Echo messages are sent to the master timing element by each peripheral timing element after a unique delay, in response to the reception of a timing packet. Loopback delay measurements are included in each timing packet for each peripheral timing element. Each peripheral timing element locks a loop using only timing packets which incur a minimum loopback delay.

Abstract: Two emitter follower transistors (260, 250), in which each transistor has an emitter coupled to one of the collectors of a differential pair structure (230, 240)to form two stacked transistor pairs (260, 230) and (250, 240). A first differential signal (IN, INX) is positive supply referenced (Vcc) and is coupled to the bases of the emitter follower transistors (250, 260). A second differential input signal (275, 295) is coupled to the bases of the differential pair transistors (230, 240). The second differential input signal (275, 295) is identical to the first input signal but also includes a voltage level shift from the positive supply (Vcc). The first and second input signal portions are coupled to the transistors which make up the stacked transistor pair (260, 230) and (250, 240) and are chosen so that they are 180 degrees out of phase.

Abstract: A fractional frequency synthesizer (100) includes a symmetrical divider (165) having an output frequency signal (135) fractionalized based on half cycles of its input frequency signal (130). The divider (165) is provided with a divisor (145) that varies based on half cycles of the output signal. Preferably, the divider (165) operates to selectively add or subtract an increment, corresponding to one half cycle of the input frequency signal (130), to a half cycle of the output frequency signal (135).

Abstract: An emitter coupled logic gate (300) avoids the use of stacked transistors by utilizing a single-ended bias input and positive feedback (320) between first and second transistors (304, 306) to achieve an inverter function. The inverter (300) can also be configured as an OR gate (500) by adding a third transistor biased by second single-ended logic input. The OR gate (500) can be configured into an exclusive OR gate (901) by converting another set of single-ended bias inputs into what can be either differential or non-differential outputs (921, 923) to be used as inputs to OR gate (919).

Abstract: A fully differential, low voltage ECL gate (300) receives complementary logic signals (A, Ax, B, Bx) and provides them to first and second differential pairs (306, 318). Collectors from different differential pairs (306) and (318) are coupled together and provided with independent current paths through load resistors, R1, (336) and R2 (338). Differential outputs (OUT, OUTx) are generated at the common collector nodes (344, 346). The load resistors (336, 338) are selected to control the gain and ensure that a minimum switching threshold (V.sub.th) is maintained under all differential input signal conditions of (A, Ax, B, and Bx) for a logical AND or OR function.

Abstract: A fully differential, low voltage ECL gate (300) receives differential input signals (A, Ax, B, Bx) and provides them to first and second differential amplifiers (306, 328). The first differential amplifier (306) amplifies and level shifts the differential input (A, Ax) to provide a differential output (OUTx). The second differential amplifier amplifies the second differential input (B, Bx) to provide an amplified output, OUT. The amplified output signal, OUT, provides a different voltage level than that provided by amplified level shifted output signal, OUTx. The amplified level shifted output (OUTx) of the first differential amplifier (306) is then compared to the amplified output (OUT) of the second differential amplifier (328) to provide either an AND gate or an OR gate function.