Patents by Inventor Piero G. Fallica

Piero G. Fallica has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5854506
    Abstract: A particle-detector is formed on a die of semiconductor material (20) comprising: first and second layers (22, 23) with a first type of conductivity (N), a third layer (21) with a second type of conductivity (P), interposed between the first and second layers (22, 23), first and second means (25, 31; 26, 32) for electrical connection with the first and second layers (22, 23), respectively, disposed on the opposite surfaces thereof to those of the junctions with the third layer (21) and third means (27, 24) for electrical connection with the third layer (21).To permit large-scale industrial manufacture, the third means (27, 24) for electrical connection with the third layer (21) comprise a region (24) with the second type of conductivity (P) which extends from the front face of the die as far as the third layer (21) and means (27) for surface electrical contact with this region.
    Type: Grant
    Filed: February 27, 1996
    Date of Patent: December 29, 1998
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventor: Piero G. Fallica
  • Patent number: 5530271
    Abstract: An integrated structure active clamp for the protection of a semiconductor power device against overvoltages includes at least one first diode and at least one second diode defined in a lightly doped layer of a first conductivity type in which the power device is also disposed. The first diode has a first electrode connected to a control electrode of the power device and a second electrode connected to a second electrode of the second diode. The second diode has a first electrode connected to a load driving electrode of the power device. The second electrode of the second diode is represented by a first buried region of a second conductivity type, which is buried in the lightly doped layer, and the first electrode of the second diode is represented by a first doped region of the first conductivity type which extends from a semiconductor top surface into the lightly doped layer to partially overlap the first buried region.
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: June 25, 1996
    Assignee: Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno
    Inventor: Piero G. Fallica