Patents by Inventor Pierpaolo RECANATINI

Pierpaolo RECANATINI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230005755
    Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.
    Type: Application
    Filed: September 12, 2022
    Publication date: January 5, 2023
    Applicants: STMicroelectronics S.r.l., STMicroelectronics (MALTA) Ltd
    Inventors: Roseanne DUCA, Dario PACI, Pierpaolo RECANATINI
  • Patent number: 11443958
    Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: September 13, 2022
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Malta) Ltd
    Inventors: Roseanne Duca, Dario Paci, Pierpaolo Recanatini
  • Patent number: 11309237
    Abstract: The present disclosure is directed to a semiconductor package including a substrate having a lower surface with a plurality of slot structures. The plurality of slot structures are multi-layer structures that encourage the formation of solder joints. The semiconductor package is desirable for high reliability applications in which each solder joint termination should be checked by visual systems to ensure a proper electrical connection has been made.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 19, 2022
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (MALTA) LTD
    Inventors: Marco Del Sarto, Alex Gritti, Pierpaolo Recanatini, Michael Borg
  • Publication number: 20210166949
    Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 3, 2021
    Applicants: STMicroelectronics S.r.l., STMicroelectronics (Malta) Ltd
    Inventors: Roseanne DUCA, Dario PACI, Pierpaolo RECANATINI
  • Publication number: 20210098355
    Abstract: The present disclosure is directed to a semiconductor package including a substrate having a lower surface with a plurality of slot structures. The plurality of slot structures are multi-layer structures that encourage the formation of solder joints. The semiconductor package is desirable for high reliability applications in which each solder joint termination should be checked by visual systems to ensure a proper electrical connection has been made.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Inventors: Marco DEL SARTO, Alex GRITTI, Pierpaolo RECANATINI, Michael BORG