Abstract: Active post-power loss discharging of capacitors is provided. In an integrated circuit having a startup behavior depending on a capacitor voltage, a discharge transistor is provided to discharge the capacitor. A power-down discharger actively drives the discharge transistor after a power supply voltage drops below a threshold. The power-down discharger may include, or be coupled to, an internal capacitance that is charged when the power supply voltage is above the threshold, thereby storing sufficient energy for later driving of the discharge transistor. A diode is employed to ensure that the loss of power does not drain away the needed energy until after the discharge has been completed. One illustrative discharging method includes: sensing a condition indicative of power supply voltage loss for an integrated circuit; and actively driving the discharge transistor into a conducting state. The sensing may include driving the discharge transistor inversely to a signal from a pin.

Abstract: Active post-power loss discharging of capacitors is provided. In an integrated circuit having a startup behavior depending on a capacitor voltage, a discharge transistor is provided to discharge the capacitor. A power-down discharger actively drives the discharge transistor after a power supply voltage drops below a threshold. The power-down discharger may include, or be coupled to, an internal capacitance that is charged when the power supply voltage is above the threshold, thereby storing sufficient energy for later driving of the discharge transistor. A diode is employed to ensure that the loss of power does not drain away the needed energy until after the discharge has been completed. One illustrative discharging method includes: sensing a condition indicative of power supply voltage loss for an integrated circuit; and actively driving the discharge transistor into a conducting state. The sensing may include driving the discharge transistor inversely to a signal from a pin.

Abstract: In an embodiment, a gate driver circuit and/or method therefor may include configuring the gate driver circuit form a drive current to supply to a gate of an MOS transistor wherein the value of the drive current is a minimum value that can be supplied to the gate without increasing a charge stored on a gate-to-source capacitance of the MOS transistor; configuring the gate driver circuit to change the value of the drive current responsively to changes of a Vgs of the MOS transistor.

Abstract: In an embodiment, a gate driver circuit and/or method therefor may include configuring the gate driver circuit form a drive current to supply to a gate of an MOS transistor wherein the value of the drive current is a minimum value that can be supplied to the gate without increasing a charge stored on a gate-to-source capacitance of the MOS transistor; configuring the gate driver circuit to change the value of the drive current responsively to changes of a Vgs of the MOS transistor.

Abstract: In one embodiment, a charge-pump controller is formed to control a value of current supplied to a load.

Abstract: In one embodiment, a charge-pump controller is formed to control a value of current supplied to a load. One embodiment of a method of forming a charge pump controller may include configuring no more than three alternately switched switches of the charge pump controller to couple to a capacitor wherein the no more than three alternately switched switches are configured to couple the capacitor in a charging configuration during a first time period and to couple the capacitor to supply a current to an LED during a second time period. Another embodiment of the method may include configuring the charge pump controller to receive a sense signal that is representative of the current and to regulate the current, substantially to a first value.

Abstract: In one embodiment, two transistors are coupled in a current mirror configuration to form a delta voltage, and an amplifier is configured to control a first current carrying electrode of each of the first and second transistors at a substantially constant voltage.

Abstract: In one embodiment, a circuit is configured to operate with a communication protocol that has at least three different signal levels wherein different sequences of the three levels identify different elements of the communication protocol. In another embodiment, a modular control block may be used to select the communication protocol and the operation of the circuit.

Abstract: In one embodiment, a circuit is configured to operate with a communication protocol that has at least three different signal levels wherein different sequences of the three levels identify different elements of the communication protocol. In another embodiment, a modular control block may be used to select the communication protocol and the operation of the circuit.

Abstract: In one embodiment, a charge-pump controller is formed to control a value of current supplied to a load.

Abstract: A power amplifier driver (16) provides control voltage inputs to power amplifier (14) at terminal (OUT). An output power control loop is implemented through directional coupler (20) and power amplifier driver (16). Power amplifier driver (16) implements a loop integration function utilizing transconductance amplifiers (60, 62) to convert a detection signal (DET) and a reference signal (REF2) to current for summing at node 58. Transconductance amplifiers (70,72) convert the error voltage generated at node (34) and bias voltage (Vmin) to current for summing at node (36) for subsequent conversion back to voltage by resistor (74). The error voltage at node (36) is buffered (26) to provide adequate current drive at terminal (OUT).

Abstract: A power amplifier driver (16) provides control voltage inputs to power amplifier (14) at terminal (OUT). An output power control loop is implemented through directional coupler (20) and power amplifier driver (16). Power amplifier driver (16) implements a loop integration function utilizing transconductance amplifiers (60, 62) to convert a detection signal (DET) and a reference signal (REF2) to current for summing at node 58. Transconductance amplifiers (70,72) convert the error voltage generated at node (34) and bias voltage (Vmin) to current for summing at node (36) for subsequent conversion back to voltage by resistor (74). The error voltage at node (36) is buffered (26) to provide adequate current drive at terminal (OUT).

Abstract: Voltage regulator (10) provides current sense comparator (18) to detect the normal and standby modes of operation for voltage regulator (10). During a normal mode of operation, current sense comparator (18) de-asserts signal (MODE), causing voltage regulator (10) to regulate the output voltage to a predetermined level. Once the current (Iin) has diminished below a predetermined value, current sense comparator (18) asserts signal (MODE) to indicate a standby mode. During the standby mode, regulator (10) regulates the output voltage (Vout) between first and second reference levels, requiring a quiescent current level much less than the quiescent current level required during normal mode, due to the deactivation of current sense comparator (18) and error amplifier (28) during standby mode. An alternate method of quiescent current reduction uses switched voltage reference (86).

Abstract: Voltage regulator (10) provides current sense comparator (18) to detect the normal and standby modes of operation for voltage regulator (10). During a normal mode of operation, current sense comparator (18) de-asserts signal (MODE), causing voltage regulator (10) to regulate the output voltage to a predetermined level. Once the current (Iin) has diminished below a predetermined value, current sense comparator (18) asserts signal (MODE) to indicate a standby mode. During the standby mode, regulator (10) regulates the output voltage (Vout) between first and second reference levels, requiring a quiescent current level much less than the quiescent current level required during normal mode, due to the deactivation of current sense comparator (18) and error amplifier (28) during standby mode. An alternate method of quiescent current reduction uses switched voltage reference (86).