Patents by Inventor Pierre Axel LAGADEC

Pierre Axel LAGADEC has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11621906
    Abstract: Disclosed is a method for test traffic generation, at test-sending switches for a network of calculation nodes, and of inspection of this test traffic, at test-receiving switches of this network, including: the generation and sending of test traffic, at least at a selected test-sending input or output port of one selected test-sending switch, sent to at least one selected test-receiving input or output port of a selected test-receiving switch, where the test traffic is generated and sent by a traffic generation component configured as an additional input of the selected test-sending input or output port, where the test traffic is inspected by a traffic inspection component configured for filtering the output of the selected test-receiving input or output port.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: April 4, 2023
    Assignee: BULL SAS
    Inventors: Vivian Blanchard, Laurent Marliac, Dominique Rigal, Pierre Axel Lagadec
  • Patent number: 11016915
    Abstract: A method for sending data, from an upstream device to a downstream device, including sending a piece of data from one among a plurality of virtual channels sharing the same input buffer memory of the downstream device, if this virtual channel uses a number of memory locations of the input buffer memory strictly less than a current ceiling. It further comprises measuring a communication latency between the upstream and downstream devices, and calculating the current ceiling from the measured latency.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: May 25, 2021
    Assignee: BULL SAS
    Inventors: Pierre Axel Lagadec, Saïd Derradji, Dominique Rigal, Laurent Marliac
  • Publication number: 20190361822
    Abstract: A method for sending data, from an upstream device to a downstream device, including sending a piece of data from one among a plurality of virtual channels sharing the same input buffer memory of the downstream device, if this virtual channel uses a number of memory locations of the input buffer memory strictly less than a current ceiling. It further comprises measuring a communication latency between the upstream and downstream devices, and calculating the current ceiling from the measured latency.
    Type: Application
    Filed: May 21, 2019
    Publication date: November 28, 2019
    Inventors: Pierre Axel LAGADEC, Saïd DERRADJI, Dominique RIGAL, Laurent MARLIAC
  • Publication number: 20180302313
    Abstract: Disclosed is a method for test traffic generation, at test-sending switches for a network of calculation nodes, and of inspection of this test traffic, at test-receiving switches of this network, including: the generation and sending of test traffic, at least at a selected test-sending input or output port of one selected test-sending switch, sent to at least one selected test-receiving input or output port of a selected test-receiving switch, where the test traffic is generated and sent by a traffic generation component configured as an additional input of the selected test-sending input or output port, where the test traffic is inspected by a traffic inspection component configured for filtering the output of the selected test-receiving input or output port.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 18, 2018
    Inventors: Vivian BLANCHARD, Laurent MARLIAC, Dominique RIGAL, Pierre Axel LAGADEC