Abstract: A data and signaling time slot transfer and processing system for a set of multiplex lines comprises a switching matrix. Its inputs are connected to n multiplex lines by switching matrix input lines. There are m serial communication controllers each connected to an input register and an output register. The outputs of the switching matrix are connected by m output lines to the input registers. Its inputs are connected by m input lines to the output registers. The matrix outputs are also connected by n switching matrix output lines to multiplex lines. A composite clock signal is applied to all the input and output registers. A further clock signal is applied to the controllers, for the purpose of changing the information reception and transmission bit rates, the information having a bit rate of 64 kbit/s and the multiplex lines functioning at 2.048 Mbit/s.

Abstract: An addressing circuit has a register search counter (20) connected to a first multiplexer (24) and to a second multiplexer (25), a memory (33) connected to the output of the first multiplexer for writing the type of processing of each register, a register counter (26) connected to the second multiplexer which is itself connected by its output to three address registers (28, 30, 32) in series. The output of the second register (30) is connected to the first multiplexer to write address the memory under the control of a write signal (CRW). The register search counter read addresses the memory and stops as soon as a register requiring rapid processing is detected; the second multiplexer receives a transfer signal (ST) to transmit the address applied to the output of the register search counter; the register counter (26) stops during the transfer signal.