Abstract: The present invention concerns a transistor of semiconductor materials of the 3-5 group on silicon of the type comprising a silicon substrate, at least one layer of semi-insulating 3-5 material and several doped layers of 3-5 group semiconductor material in which is defined at least one conducting channel equipped with a gate metallization, each channel being situated between two access regions alternately known as source and drain, each source and drain regions with a metallization, one of the two access regions to a channel being electrically and thermally connected to the silicon substrate. In accordance with the invention, the transistor comprises between the silicon substrate and the semi-insulating layer of 3-5 group semiconductor material, at least one buffer layer of intrinsic silicon.

Abstract: According to this process, P.sup.+ type parallel bars are implanted in a N type silicon substrate. Thereafter an oxidation above the implanted zones is carried out, then a uniform layer of polycrystalline silicon is deposited that contacts the N type silicon substrate by being directly isolated from the P.sup.+ type grid bars.The present invention allows to manufacture particularly miniaturized vertical junction field-effect transistor structures by a simple process.

Abstract: This transistor comprises a first main surface of alternating source and gate strips. A gate metallization rests on the gate strips and a source metallization rests on a polycrystalline silicon rail formed above the source strips. Such a device can be manufactured by entirely self-aligned methods and is applicable particularly to the very high frequency range up to a few dozen gigahertz.