Patents by Inventor Pierre Chor-Fung Chia

Pierre Chor-Fung Chia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8689081
    Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: April 1, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Andy Yu, Pierre Chor-Fung Chia, ShiJie Wen, Jie Xue
  • Publication number: 20130139033
    Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 30, 2013
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Andy Yu, Pierre Chor-Fung Chia, ShiJie Wen, Jie Xue
  • Patent number: 8421237
    Abstract: In one embodiment, an apparatus includes a first memory layer oriented in a first planar orientation, a second memory layer oriented in a second planar orientation, a third memory layer oriented in the first planar orientation; and a connector that is connected to the first memory layer at an electrical contact of the first memory layer and to the third memory layer at an electrical contact of the third memory layer, where the connector is unconnected to the second memory layer. At least one of the electrical contact of the first memory layer and the electrical contact of the third memory layer comprises a through-layer via. The second planar orientation is angularly offset a predetermined number of degrees from the first planar orientation.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: April 16, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Pierre Chor-Fung Chia, Li Li
  • Publication number: 20130009318
    Abstract: In one embodiment, an apparatus includes a first memory layer oriented in a first planar orientation, a second memory layer oriented in a second planar orientation, a third memory layer oriented in the first planar orientation; and a connector that is connected to the first memory layer at an electrical contact of the first memory layer and to the third memory layer at an electrical contact of the third memory layer, where the connector is unconnected to the second memory layer. At least one of the electrical contact of the first memory layer and the electrical contact of the third memory layer comprises a through-layer via. The second planar orientation is angularly offset a predetermined number of degrees from the first planar orientation.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 10, 2013
    Inventors: Pierre Chor-Fung Chia, Li Li