Abstract: The invention relates to a method for producing seals made of polyurethane, in which (a) aliphatic polyisocyanate, (b) compounds containing at least two isocyanate-reactive groups, (c) catalysts, (d) antioxidants and/or light stabilizers, and, optionally, (e) blowing agents, and (f) auxiliary agents and/or additives are mixed to form a reaction mixture, and the reaction mixture is allowed to complete the reaction to form polyurethane. The seal made of polyurethane has a Shore A hardness of less than 90 and a density of at least 850 g/L. The polymeric compounds having groups reactive toward isocyanate include b1) polyetherols having a functionality of 2 to 4 and a hydroxyl number of 20 to 100 mg KOH/g, b2) hydrophobic polyols having an OH number of less than 180 mg KOH/g and a functionality of greater than 2 to 3, and b3) chain extenders.

Abstract: The invention relates to a method for producing seals made of polyurethane, in which (a) aliphatic polyisocyanate, (b) compounds containing at least two isocyanate-reactive groups, (c) catalysts, (d) antioxidants and/or light stabilizers, and, optionally, (e) blowing agents, and (f) auxiliary agents and/or additives are mixed to form a reaction mixture, and the reaction mixture is allowed to complete the reaction to form polyurethane. The seal made of polyurethane has a Shore A hardness of less than 90 and a density of at least 850 g/L. The polymeric compounds having groups reactive toward isocyanate include b1) polyetherols having a functionality of 2 to 4 and a hydroxyl number of 20 to 100 mg KOH/g, b2) hydrophobic polyols having an OH number of less than 180 mg KOH/g and a functionality of greater than 2 to 3, and b3) chain extenders.

Abstract: A process for the production of micro-cellular or non-cellular, light-stable elastomeric, flexible or semi-flexible polyurethane moldings which are especially suited for window encapsulation applications from a reaction mixture by the reaction injection molding process, wherein: A) an isocyanate component containing an isophorone diisocyanate (IPDI) trimer/monomer mixture having an NCO content of from 24.

Abstract: A combined sense amplifier and latching circuit receives an input signal (VIN) at an input terminal (22). A sense amplifier includes a gated-loop type master latch (ML) having two cascaded inverters (I12, I13) with a common node (I) coupled therebetween and a control device (TG4) in the master latch loop controlled by a gating signal (55A). A reference voltage generator generates a reference voltage (VREF). The two inverters are biased between a first supply voltage (Vdd) having a magnitude greater than the reference voltage and either a second supply voltage (GND) or the reference voltage depending on the value of the gating signal. The input terminal is connected to the input of one of the inverters. A gated-loop slave latch (SL) is connected in series with the sense amplifier and includes two cascaded inverters (I14, I15) with a common node (M) coupled therebetween and a control device (P15) in the slave latch loop controlled by the gating signal.

Abstract: A reprogrammable logic fuse (RLF) based on a 6 device standard Static Random Access Memory (SRAM) cell includes a storage element comprised of four cross coupled FETs. A fifth FET is mounted in a transmission gate configuration between the bit line and a first common node of the storage element. Its gate electrode is connected to the word line. This FET is used to write the appropriate control data in the storage element for bit personality store. A sixth FET is also mounted in a transmission gate configuration between the second common node of the storage element and an output line. Its gate electrode is connected to the input line. This sixth FET ensures that a logical function, e.g. AND/NAND is achieved between the signals available at the second common node and on the input line. Other configurations of said sixth FET are allowed. These reprogrammable logic fuses may be disposed in matrixes to constitute reloadable logic arrays and Reloadable PLAs (RPLAs).

Abstract: In combination with an electronic memory of the type having a plurality of memory cells (CA, . . . CN) connected between two bit lines (BLT, BLC) having inherent bit line capacitances (C1, C2), there is disclosed an improved sense amplifier (15) comprised of two stages. A first stage (16) includes a first clocked latch (5) having an enable device (T5), gated by a first control signal (SSA) and bit switches (T6, T7) connected between the common nodes (6, 7) of said first clocked latch and said bit lines, and gated by a bit switch control signal (BS) to provide an output signal on first data lines (DLT, DLC). A second stage (17) includes a second clocked latch (20) having an enable device (T24) gated by a second signal (SL) and data switches (T28, T29) connected between second data lines (DT, DC) at the same potential as data output nodes (21, 22) of said second clocked latch and said first data lines (DLT, DLC).

Abstract: A semiconductor memory device including a pair of bit lines (BL, BL) having relatively high stray capacitances (C1, C2), a word line (WL), and a memory cell (MC1) connected to the bit lines and word line for selection by an address signal, and a restore circuit comprising a coupling/equalizing circuit (12) controlled by a BLR clock and a reference voltage generator (51) for quickly restoring the bit lines. The reference voltage generator (51) comprises both static and dynamic current sources. The static current source consists of a small N MOS transistor (N52) operating as a resistor load, while the dynamic current source consists of at least one small P MOS transistor (P'53, . . . ), connected in parallel with the N MOS transistor, and gated with a clock (BCC', . . . ) derived from the BLR clock, so that the P MOS transistor is turned ON during the restore time. An additional N device (N54) may be inserted between the reference line (RL) and ground (GND).