Abstract: A mechanism that captures and reports interrupt events occurred in various portions of a network interface controller. As different clocks control these interface controller portions, the interrupt request signals corresponding to the interrupt events are created in different clock domains. The first stage of the mechanism for capturing and reporting interrupt events detects interrupt events having different duration, and produces an interrupt synchronizing signal asserted during at least one period of a local clock signal. The second stage serves as a positive edge detector to produce an interrupt positive edge detect signal asserted during three clock periods. The third stage supports a read operation performed by a host signal corresponding to the detected interrupt event to read an interrupt request.

Abstract: A system for tracing read and write accesses to selected registers is provided in a network interface. The system has a read trace register containing a separate bit for each register to be monitored for read access by an external CPU. A write trace register is provided with a bit for each register to be monitored for write access by the CPU. When the CPU performs read or write access to a monitored register, a decoder that decodes an address signal from the CPU produces a trace select signal supplied to the read trace register and/or write trace register. In response to the trace select signal, the bit representing the monitored register is set to a predetermined logic state indicating that the monitored register was accessed by the CPU for reading and/or writing.

Abstract: Circuit and method is disclosed which prevents contention on a pulse-code modulated (PCM) bus, when different drivers are transmitting during adjacent time slots. The driver circuit switches automatically from a strong driver to a weak driver depending on whether a signal level is merely repeating or whether the level is transiting. Also the driver always employs the strong driver at the onset of transmission.