Abstract: An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Stacked I-Cell (SIC). The SIC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SIC is made up of a polysilicon storage node structure having a I-shaped cross-sectional upper portion with a lower portion extending downward and making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SIC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having an adjustable I-shaped cross-section, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.

Abstract: The present invention develops a container capacitor by forming a first insulative layer over conductive word lines; forming an opening between neighboring conductive word lines; forming a conductive plug between neighboring parallel conductive word lines; forming a planarized blanketing second insulating layer over the first insulative layer and the conductive plug; forming an opening into the second insulating layer, the opening thereby forming a container shape; forming a conductive spacer adjacent the wall of the container form, the conductive spacer having inner and outer surfaces; removing the second insulating layer, thereby exposing the outer surface of the conductive spacer; forming a layer of hemispherical grained conductive material superjacent the inner and outer surfaces of the conductive spacer; forming insulating spacers adjacent the inner and outer surfaces of the hemispherical grained conductive material; patterning the hemispherical grained conductive material to form a separate conductive c

Abstract: This invention relates to semiconductor circuit memory storage devices and more particularly to a process to develop three-dimensional stacked capacitor cells using a high dielectric constant material as a storage cell dielectric and a combination of conductively doped polysilicon and metal silicide as the capacitor plates of a storage cell for use in high-density dynamic random access memory (DRAM) arrays. The present invention teaches how to fabricate three-dimensional stacked capacitors by modifying an existing stacked capacitor fabrication process to construct the three-dimensional stacked capacitor cell incorporating a high dielectric constant material as the cell dielectric that will allow denser storage cell fabrication with minimal increases of overall memory array dimensions. A capacitance gain of 3 to 10.times. or more over that of a conventional 3-dimensional storage cell is gained by using a high dielectric constant material as the storage cell dielectric.

Abstract: A lateral extension stacked capacitor (LESC) using a modified stacked capacitor storage cell fabrication process. The LESC is made up of polysilicon structure, having a spherical ended v-shaped cross-section. The storage node plate of the LESC is overlaid by polysilicon with a dielectric sandwiched in between and connects to an access device's active area via a buried contact. The plate extends to an adjacent storage node but is isolated from the adjacent node by less than the critical resolution dimension of a given lithographic technology. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.

Abstract: A stacked v-cell (SVC) capacitor using a modified stacked capacitor storage cell fabrication process. The SVC capacitor is made up of polysilicon structure, having a v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 70% without enlarging the surface area defined for a normal stacked capacitor cell.

Abstract: The present invention introduces an effective way to produce a thin film capacitor utilizing a high dielectric constant material for the cell dielectric through the use of a single transition metal, such as Molybdenum, for a bottom plate electrode which oxidizes to form a highly conducting oxide. Using Molybdenum, for example, will make a low resistive contact to the underlying silicon since Molybdenum reacts with silicon to form MoSix with low (<500 .mu..OMEGA.-cm) bulk resistance. In addition, Mo/MoSix is compatible with present ULSI process flow or fabricating DRAMs and the like.

Abstract: The present invention introduces a method to fabricate an active PMOS thin film transistor (or p-ch TFT) having an epitaxially grown channel region for high performance operation characteristics. Typically this p-ch TFT device would be fabricated overlying an NMOS active device, thereby becoming an active load (or pullup) to an NMOS device used is such applications as creating a memory cell in static random access memories (SRAMs). Conductivity types (p-type or n-type) may be interchanged to construct an n-ch TFT coupled with a PMOS active device if so desired. The fabrication of the TFT of the present invention may be used to form a CMOS inverter or simply an active pullup device when integrated into conventional CMOS fabrication processes.

Abstract: An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Stacked H-Cell (SHC). The SHC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SHC is made up of a polysilicon storage node structure having a H-shaped cross-sectional upper portion with a lower portion extending downward and making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SHC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having an H-shaped cross-section, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.

Abstract: A dynamic random access memory cell in which a silicon-germanium alloy layer having a rough surface morphology is utilized for the capacitive surface of the storage-node plate of the cell capacitor. To create a DRAM array having such cells, a silicon-germanium alloy is deposited, typically via rapid thermal chemical vapor deposition, on top of a single crystalline silicon or polycrystalline silicon storage-node plate layer under conditions which favor three-dimensional growth in the form of macroscopic islanding (i.e., a high concentration of germanium in precursor gases and relatively high deposition temperature). A cell dielectric layer, which exhibits the property of bulk-limited conduction (e.g., silicon nitride), is utilized. Except for the deposition of the silicon-germanium alloy, array processing is conventional.

Abstract: A multi-poly spacer, double-plate, stacked capacitor or MDSC using a modified stacked capacitor storage cell fabrication process. The MDSC is made up of a rectangular boxed-shaped polysilicon storage node structure, having multiple poly post residing in a buried contact used to connect the MDSC to an active area. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed MDSC. Developing the MDSC from a planarized surface allows the capacitor to be fabricated with only 2 photomask steps. With the 3-dimensional shape and a texturized surface of a polysilicon storage node plate, substantial capacitor plate surface area of 100% or more is gained at the storage node.

Abstract: An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Double Ring Stacked Cell or DRSC. The DRSC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The DRSC is made up of a polysilicon storage node structure having circular polysilicon ringed upper portion centered about a lower portion that makes contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed DRSC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having double polysilicon rings, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.

Abstract: A stacked textured container capacitor (STCC) using a modified stacked capacitor storage cell fabrication process. The STCC is made up of a texturized polysilicon structure, having an elongated u-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. With the 3-dimensional shape and texturized surface of a polysilicon storage node plate substantial capacitor plate surface area of 200% or more is gained at the storage node.

Abstract: This invention relates to semiconductor circuit memory storage devices and more particularly to a process to develop three-dimensional stacked cell capacitors using a PZT ferroelectric material as a storage cell dielectric for use in high-density dynamic random access memory (DRAM) arrays. The present invention employs using PZT ferroelectric for the storage cell dielectric in three-dimensional stacked capacitor technology and develops an existing stacked capacitor fabrication process to construct a PZT three-dimensional stacked capacitor cell (the EFSC) that will allow denser storage cell fabrication with minimal increases of overall memory array dimensions. A capacitance gain of 3 to 10X or more over that of a conventional 3-dimensional storage cell is gained by using PZT ferroelectric as the storage cell dielectric.

Abstract: A method is disclosed for forming a capacitor on a semiconductor wafer. A first electrically conductive layer is applied atop the wafer and engages exposed active areas. A first dielectric layer is next applied. The first dielectric and conductive layers are then patterned to define an outline for the lower capacitor plate. A second dielectric layer, having an etch rate which is slower than the first, is then applied and planarized or otherwise etched down to the first dielectric layer. The first dielectric layer is then etched down to the first conductive layer to produce upwardly projecting walls of second dielectric material surrounding the lower capacitor plate outline. A second electrically conductive layer is then applied. It is then anisotropically etched to provide a first electrically conductive wall extending upwardly from the first conductive layer. A third dielectric layer is then applied.

Abstract: An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to hereinafter as a stacked E cell or SEC. The SEC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SEC is made up of a polysilicon storage node structure having an E-shaped cross-sectional upper portion and a lower portion making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SEC capacitor. With the 3-dimensional shape and a texturized surface of a polysilicon storage node plate, substantial capacitor plate surface area of 3 to 5X is gained at the storage node.

Abstract: A method is disclosed for forming a capacitor on a semiconductor wafer which utilizes top and back sides of a capacitor node for capacitance maximization. First and second dielectric layers, having different etch rates, are applied atop the wafer, and a contact opening is etched therethrough. Poly is applied and etched to begin formation of one node of the capacitor. A layer of oxide is then formed atop the poly capacitor node. The first dielectric layer is then etched, leaving a projecting or floating capacitor node which is surrounded by the second dielectric material and oxide formed thereatop. The surrounding material is then etched, the capacitor dielectric applied, and the poly of the second capacitor nod applied and selectively etched.

Abstract: A method of forming digit lines on a semiconductor wafer having integrated circuits comprises the following consecutive steps:selectively processing the wafer to produce a desired array of dynamic random access memory cells having associated word lines and exposed active areas, the word lines being defined by electrically conductive regions comprised of a polysilicon/high conductive material sandwich structure and having side and top electrically insulated regions comprised of oxide;providing a layer of doped epitaxial monocrystalline silicon atop exposed active areas to a height which is below the uppermost portions of the electrically insulated regions atop the word lines, and above the height of the uppermost portions of the word line electrically conductive regions;providing a layer of electrically insulating oxide atop the wafer, the electrically insulating layer having a lowest point which is higher than the height of the doped epitaxial silicon layer;planarizing the electrically insulating layer by rem