Abstract: It is an object of the present invention to provide a logic program comparison method which makes it possible to do verification by comparing parameterized logic programs and which increases the efficiency of the verification. The keyboard 1 and the input section 4 read two logic programs. The conversion section 5 converts the logic programs into the first and second finite state machine descriptions. The comparison section 6 determines whether there exists an equivalence between the states, between input values, and between output values of the first and second descriptions, and determines whether both descriptions produce respective outputs values deemed equal for all respective inputs deemed equal, for all respective states deemed equal. The result of the comparison is output through the output section 7 and the display unit 2.