Abstract: A demodulator for binary messages of the diphase type comprises a sampling circuit controlled by a local clock whose cycle is approximately 1/n.sup.th of the bit length of the incoming signals (with n=8 in a specific instance), this circuit deriving (n-2) samples from each message bit which are then analyzed in a programmed memory to determine whether the bit being sampled has one of six acceptable configurations, namely a bit of logical value "0" or "1" in either a normal, a leading or a lagging position with reference to a decoding interval T equaling n clock cycles. If a different configuration is detected, an error signal is generated. The decoding interval is measured by a counter, stepped by the local clock, which is adjusted by recalibrating commands from the programmed memory to shorten or lengthen the next decoding interval when a bit is found to lead or lag by a full clock cycle, thereby restoring the normal relative time position of the message bits and the decoding interval.