Abstract: A method includes receiving, by a first microprocessor, a request of modification of a content of a first memory of the first microprocessor, the first memory being accessible only by the first microprocessor. The method includes accessing, by the first microprocessor, first data associated with the request and a signature generated from the first data with an asymmetric cipher algorithm. The first data and the signature are available in a second memory of a second microprocessor, and the first data is representative of a modification to be applied to the content of the first memory. The modification is representative of a modification of a set of services exposed by the first microprocessor. The method includes verifying, by the first microprocessor, authenticity of the first data based on the signature; and modifying the content of the first memory according to the first data, the modifying being conditioned by the verifying.

Abstract: A hardware monitor circuit includes an electronic control circuit coupled to a processing unit. The electronic control circuit generates multi-bit protection codes and directs operations of the hardware monitor circuit. A bus interface is coupled to an address bus of the processing unit, and the bus interface passes signals associated with a stack structure of the processing unit. The stack structure is arranged to store the multi-bit protection codes in an internal memory coupled to the processing unit. Comparators in the hardware monitor circuit are arranged to accept values from the internal memory and gating logic coupled to the comparators is arranged to generate an error signal when it detects that an address on the address bus read via the bus interface is equal to an address stored in the internal memory. Upon generating the error signal, the processing unit is placed in a secure mode.

Abstract: A method includes receiving, by a first microprocessor, a request of modification of a content of a first memory of the first microprocessor, the first memory being accessible only by the first microprocessor. The method includes accessing, by the first microprocessor, first data associated with the request and a signature generated from the first data with an asymmetric cipher algorithm. The first data and the signature are available in a second memory of a second microprocessor, and the first data is representative of a modification to be applied to the content of the first memory. The modification is representative of a modification of a set of services exposed by the first microprocessor. The method includes verifying, by the first microprocessor, authenticity of the first data based on the signature; and modifying the content of the first memory according to the first data, the modifying being conditioned by the verifying.

Abstract: A hardware monitor circuit includes an electronic control circuit coupled to a processing unit. The electronic control circuit generates multi-bit protection codes and directs operations of the hardware monitor circuit. A bus interface is coupled to an address bus of the processing unit, and the bus interface passes signals associated with a stack structure of the processing unit. The stack structure is arranged to store the multi-bit protection codes in at least one internal memory coupled to the processing unit. A plurality of comparators in the hardware monitor circuit are arranged to accept values from the at least one internal memory and gating logic coupled to the plurality of comparators is arranged to generate an error signal when it detects that an address on the address bus read via the bus interface is equal to an address stored in the at least one internal memory. Upon generating the error signal, the processing unit is placed in a secure mode.

Abstract: A first operation of comparison of the first initial operand with the second initial operand uses at least one comparison operator in such a way as to obtain a first final result word. A second operation of comparison of the second initial operand with the first initial operand uses the at least one comparison operator in such a way as to obtain a second final result word. Another operation checks the values of the bits of the two final result words in relation to a part at least of r combinations of reference values taken from possible combinations of values of these two final result words. These reference combinations represent a valid result of comparison of the two operands including an equality, a relationship of inferiority and a relationship of superiority between the two operands.

Abstract: A first operation of comparison of the first initial operand with the second initial operand uses at least one comparison operator in such a way as to obtain a first final result word. A second operation of comparison of the second initial operand with the first initial operand uses the at least one comparison operator in such a way as to obtain a second final result word. Another operation checks the values of the bits of the two final result words in relation to a part at least of r combinations of reference values taken from possible combinations of values of these two final result words. These reference combinations represent a valid result of comparison of the two operands including an equality, a relationship of inferiority and a relationship of superiority between the two operands.

Abstract: A microprocessor includes a central processing unit, at least one call stack, a stack pointer, an address bus, and a data bus. The microprocessor further includes a hardware monitor configured to supply protection codes, insert the protection codes in the stack or let the central processing unit insert them, and then generate an error signal in response to an attempt to modify a protection code present in the stack.

Abstract: A method and an element of ciphering by an integrated processor of data to be stored in a memory, including applying a ciphering algorithm which is a function of a key specific to the integrated circuit and of an initialization vector, and of memorizing at least the ciphered data, the initialization vector depending at least on the address of storage of the data in the memory.

Abstract: A method and an element of ciphering by an integrated processor of data to be stored in a memory, including applying a ciphering algorithm which is a function of a key specific to the integrated circuit and of an initialization vector, and of memorizing at least the ciphered data, the initialization vector depending at least on the address of storage of the data in the memory.

Abstract: An electromagnetic accelerometer including a stationary stator element (12) associated with a movable polar element (14) securable to an external member (2), the stationary stator element (12) and the movable polar element (14) forming a magnetic circuit and defining between them at least two gaps (51), a magnet (5) helping to create magnetic field lines in the magnetic circuit, a coil (6) and a mechanism for energizing the coil for controlling the displacement of the movable polar element (14) through electromagnetic induction phenomena. The electromagnetic accelerometer further includes an adjustment polar element (15) for placing the movable polar element (14) in an adjusted position with respect to that of the stationary stator element (12), by deviating the magnetic field lines.

Abstract: An electromagnetic accelerometer includes a peripheral frame, a mass suspended from the peripheral frame, a plurality of strain gauges configured to detect displacement of the mass, and a magnetic motor. The magnetic motor includes a first pole piece defining a chamber, a second pole piece positioned in the chamber and coupled to the mass, a permanent magnet coupled to the first pole piece, and a coil coupled to the first pole piece. The permanent magnet and the coil surround at least a portion of the second pole piece.

Abstract: The invention provides a method for controlling a brushless motor, with windings connected in star (`wye`) formation, including the steps of periodically applying a supply voltage between first and second windings, detecting the presence of a current in a third winding, and an instant of cessation of that current, monitoring the value of a back emf induced in the third winding and detecting a zero crossing point of the back emf, timing a predetermined delay from the zero crossing point, and after the end of the delay, applying the supply voltage to other windings. The invention also provides a method for use with motors having windings connected in delta formation.

Abstract: An electromagnetic accelerometer includes a moving mass suspended to a peripheral frame and associated with stress gauges forming sensors for detecting the displacement of the moving mass which supports a coil, and a permanent magnet which is associated with a magnetic circuit formed by two pole pieces defining two air-gaps for channeling the magnetic field of the magnet. The moving mass includes a central recess having a surface at least equal to the surface of a free extremity of a first pole piece of the magnetic circuit and forming a shoulder for receiving the coil, the free extremity of the shoulder leading inside the air-gaps.