Patents by Inventor Pierre GUIRONNET DE MASSAS

Pierre GUIRONNET DE MASSAS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PROCESSOR WITH A CONFIGURABLE DISTRIBUTION OF PRIVILEGED RESOURCES AND EXCEPTIONS BETWEEN PROTECTION RINGS
    Publication number: 20210200904
    Abstract: A processor having a plurality of protection rings and comprising a protection ring management system in which the attributions of exceptions or privileged resources to protection rings are defined by a programmable table.
    Type: Application
    Filed: December 31, 2020
    Publication date: July 1, 2021
    Inventors: Pierre GUIRONNET DE MASSAS, Vincent RAY, Benoit DUPONT DE DINECHIN
  • Hardware synchronization barrier between processing units
    Patent number: 9766951
    Abstract: A method for synchronizing multiple processing units, comprises the steps of configuring a synchronization register in a target processing unit so that its content is overwritten only by bits that are set in words written in the synchronization register; assigning a distinct bit position of the synchronization register to each processing unit; and executing a program thread in each processing unit. When the program thread of a current processing unit reaches a synchronization point, the method comprises writing in the synchronization register of the target processing unit a word in which the bit position assigned to the current processing unit is set, and suspending the program thread. When all the bits assigned to the processing units are set in the synchronization register, the suspended program threads are resumed.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: September 19, 2017
    Assignee: KALRAY
    Inventors: Thomas Champseix, Benoît Dupont De Dinechin, Pierre Guironnet De Massas
  • HARDWARE SYNCHRONIZATION BARRIER BETWEEN PROCESSING UNITS
    Publication number: 20150339173
    Abstract: A method for synchronizing multiple processing units, comprises the steps of configuring a synchronization register in a target processing unit so that its content is overwritten only by bits that are set in words written in the synchronization register; assigning a distinct bit position of the synchronization register to each processing unit; and executing a program thread in each processing unit. When the program thread of a current processing unit reaches a synchronization point, the method comprises writing in the synchronization register of the target processing unit a word in which the bit position assigned to the current processing unit is set, and suspending the program thread. When all the bits assigned to the processing units are set in the synchronization register, the suspended program threads are resumed.
    Type: Application
    Filed: May 26, 2015
    Publication date: November 26, 2015
    Inventors: Thomas CHAMPSEIX, Benoît DUPONT DE DINECHIN, Pierre GUIRONNET DE MASSAS