Abstract: A circuit arrangement synchronizes data transfers between a first device and a second device operating at different data rates. The circuit arrangement is comprised of a plurality of registers for storing data received from a device with the higher data rate. A scan logic circuit counts strobe pulses provided by the device with the higher data rate when data is available on its output bus. Selected counts from the scan logic circuit cause data on the output bus to be sequentially transferred into the plurality of registers. Strobe latch logic keeps track of the loading sequence and, in response thereto, select logic and gate arrangement causes the content of a selected register to be transferred to an output register at each clock signal of the slower device.

Abstract: A system for cascading data switches in a communication node allows for transfer of data among a plurality of adapters (30-i), expanding a moderate low cost switch 31-1 with additional hardware (31-2, 31-3, 31-4) to interconnect more adapters. The data transfers are performed by a plurality of Burst Relaying Cascaders (32-i) which connect the plurality of switches (31-i). A similar interface connect each adapter to the switch. A set of address information is used by the system to route the data from the source adapter to the target adapter, allowing navigation among the intermediate switches. Each interface contains a table where the address of every adapter of the whole system could be constructed dynamically at each communication node configuration.

Abstract: A memory interface mechanism is driven from the memory controller side which comprises lines which are shared by the memory user devices and lines which are specific to the memory user devices. The shared lines are the address and data bus lines the byte select lines, the data and address clock lines and the last operation line. The specific lines are the request lines, the address user indicator lines and data user indicator lines. A user initiates a memory operation by activating its request line and then waits for the activation by the memory interface control circuit for the activation of the address and data user indicator lines. The user controls the address and data transfer count and ends the transfer by activating the last operation line. Then it waits for the deactivation by the memory controller of the address and data user indicator lines to present a new request, if any. Thus the memory transfer is memory driven which allows full advantage to be taken of a page mode facility of the memory.

Abstract: Disclosed is a memory access control device for a memory organized in 2.sup.n byte words and having the capability of addressing each byte in a word under control of byte select signals (BS), through an m-byte wide bus 22, with 2.sup.n /m being an integer k, to write or read data byte bursts comprising a variable count of bytes. For writing, k sets of m bytes received from bus 22 are stored into 2.sup.n registers 40 during each bus period T; they are then transferred into buffer 30 which comprises successive location of 2.sup.n bytes positions, through an alignment and control logic 42, which causes the buffer to be written in such a way that it maps the data arrangement in memory. This depends upon the least significant bits of the memory starting address determining the byte location within the memory words. Once the complete data burst is written into the buffer, the buffer content is transferred to the memory.

Abstract: Described is a sequencing device comprising a plurality of shift register stages, a plurality of switches and an output bus which couples the outputs from the shift register stages to inputs of the switches. Each shift register stage includes a data input port coupled to a selected switch, a clock input port coupled to a clock control signal line and a clear input port coupled to a clear control signal line. The sequencing device may be set in at least one of a plurality of states by external events that are provided as input signals to the sequencing device through input bus (10).