Abstract: A library of waivable images with corresponding waiver constraints is generated. Each of the waivable images is an image of a region of a reference design layout including a raw error as determined by an optical rule checks (ORC) program and does not require a correction for printability on a photoresist layer. A list of raw errors is generated by running the ORC program on a target design layout. Error region images corresponding to the list of raw errors are generated by selecting a region of the target design layout around points corresponding to the raw errors. A list of matches between the library of waivable images and the error region images is generated. By removing a subset of raw errors that correspond to a subset of the list of matches from the list of raw errors, a list of real errors is generated.

Abstract: A method and system is provided to use the same design manipulation processes for both chip design and kerf design. Concurrent generation of kerf designs and chip designs provides a consistent, accurate, and repeatable process. Improved quality of wafer testing results because the data in the kerf matches data in the chip. The total cycle time for mask manufacturing is reduced because kerf build is accomplished prior to start of the mask manufacturing process. Also provided is the use of load balancing across multiple servers during kerf and chip design to optimize computing resources.

Abstract: A method and system is provided to use the same design manipulation processes for both chip design and kerf design. Concurrent generation of kerf designs and chip designs provides a consistent, accurate, and repeatable process. Improved quality of wafer testing results because the data in the kerf matches data in the chip. The total cycle time for mask manufacturing is reduced because kerf build is accomplished prior to start of the mask manufacturing process. Also provided is the use of load balancing across multiple servers during kerf and chip design to optimize computing resources.

Abstract: A method, system and program product for generating a process aid on a wafer are disclosed. A “process aid” can be any device provided on a wafer that assists in some process step, but does not ultimately make up part of a usable die. The invention implements libraries of technology design rules, and process aid parameters, and a process aid instruction file library to allow automatic generation of a process aid according to the technology design rules and parameters. As a result, all the inputs required to build a process aid are available up front, which allows the invention to automatically adjust kerf designs to conform to the new technologies. In addition, the invention provides documentation indicating the inputs and details of the process aid produced.

Abstract: A diagnostic system and method for testing an integrated circuit during fabrication thereof. The diagnostic system has at least one integrated circuit chip that has an electrical signature associated with it; a sacrificial circuit that is adjacent to the integrated circuit chip and has a known electrical signature associated with it and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit indicates that the integrated circuit chip is mis-designed. The diagnostic system further includes a semiconductor wafer that has a plurality of integrated circuit chips and a kerf area separating one integrated circuit chip from another integrated circuit chip. A mis-designed integrated circuit chip has abnormally functioning circuitry.