Abstract: A memory sub-system, having: a host interface configured to operate on a computer bus; non-volatile memory cells; and a controller. In response to a command to identify information about the memory sub-system, the controller is to provide structured data indicating that the memory sub-system supports sub block access and specifying a sub block granularity level for the sub block access. In response to an access command with a sub block descriptor embedded within the access command, the controller is to determine, based on the sub block descriptor provided within the access command, a portion of a logical block identified by the access command and implemented using a subset of the non-volatile memory cells. An operation is performed on the portion of the logical block according to an opcode specified by the access command.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller or processing device of a host system adds an entry to a local shared work queue of the host system. The entry includes an NVMe command to be executed by the SSD. The entry also includes an address for a shared work queue of the SSD. The controller or processing device writes the command to the shared work queue of the SSD using a PCIe memory write. The command is then executed by the SSD.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, a memory sub-system (e.g., SSD) includes: at least one non-volatile memory device (e.g., flash memory); and at least one controller configured to: provide access to at least one shared work queue by exposing a portion of memory to a host system (e.g., GPU); receive, in the shared work queue, a command from the host system (e.g., NVMe command over PCIe fabric); and in response to receiving the command, copy the command to an internal command queue (e.g., queue of the SSD) for execution to access the non-volatile memory device according to an operation (e.g., read/write) identified in the command.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller of the SSD receives, in a shared work queue, commands from a host system (e.g., CPU). Each command specifies an address space identifier (e.g., PASID). In response to receiving the command, the controller executes the command to perform an operation (e.g., read or write) identified in the command. The address space identifier is used (e.g., by a DMA engine) when performing a data transfer as part of the operation.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes NAND flash memory. A controller of a host system writes an NVMe command to the SSD using a PCIe transaction layer packet. The command is written using either a deferred memory write or a memory write according to the PCIe standard. The command is written to the SSD either directly or via a local shared work queue of the host system.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory systems. In one approach, an NVMe solid-state drive (SSD) includes NAND flash memory. A controller of a host system writes NVMe commands to the SSD using a PCIe transaction layer packet. The host system can selectively configure a shared work queue interface of the SSD. A host/processor sends a get feature command to determine whether an SWQ interface is supported by the SSD. If the SSD supports the SWQ interface, then the SSD provides a response that identifies the resources provided by an NVMe controller in the SSD for use of the SWQ feature. The host/processor can send a command to enable/disable the SWQ feature using a set feature command. A queue pair can also be used whether the SWQ feature is enabled or disabled.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller receives, from a submission queue, commands configured with a predefined field, wherein the predefined field includes a command identifier. The SSD is reconfigured so that the controller receives, in a shared work queue, commands from processes executing on a host system. Each command is configured with the same predefined field (e.g., at the same Dword location according to the NVMe 2.0 specification), but the predefined field is repurposed so that its content includes at least a portion of an identifier for an address space (e.g., PASID) of the host system used by the process. Each command also may include a completion address and a phase bit.

Abstract: Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller of the SSD receives, in a shared work queue, commands from a host system (e.g., GPU). Each command specifies an address for a completion record. In response to receiving the command, the controller executes the command to perform an operation (e.g., read or write) identified in the command. Then, the controller writes the completion record to a location in main memory of the host system at the address.

Abstract: A memory sub-system, having: a host interface configured to operate on a computer bus; non-volatile memory cells; and a controller to store, in a vendor specific log page, data indicating that the memory sub-system supports sub block access and providing a sub block granularity level for the sub block access. After receiving, from the host system, an access command with a sub block descriptor configured to identify a portion of a logical block identified by the access command, the controller is to transfer, over the computer bus according to an opcode provided in the access command, data for the portion of the logical block without transferring over the computer bus data of the logical block outside of the portion of the logical block identified by the sub block descriptor.

Abstract: A memory sub-system, having: a host interface operatable on a computer bus; a non-volatile memory; and a controller. In response to a request to create a first namespace, the controller create the first namespace and a second namespace having a same storage capacity as the first namespace. The first namespace has a first granularity level; and the second namespace has a second granularity level different from the first granularity level. The first namespace and the second namespace represent a storage capacity provided by a same set of storage resources in the memory sub-system. The controller maintains a mapping between logical addresses defined in the first namespace and physical addresses of the set of storage resources, and process access to addresses in the second namespace via the mapping between logical addresses defined in the first namespace and physical addresses of the set of storage resources.

Abstract: A system includes a memory device, and a processing device, operatively coupled with the memory device, to perform operations including detecting a failure of a key-value store, identifying a non-filled zone of the memory device resulting from the failure, wherein the non-filled zone stores, in the key-value store, at least one of: an uncommitted key block or an uncommitted value block, and recovering the non-filled zone to obtain a recovered zone.

Abstract: A system and method for reordering data blocks received from a zone of a memory device. An example method includes sending, by a host system to a memory sub-system comprising a memory device, a plurality of write commands; receiving, by the host system from the memory sub-system, block allocation metadata, wherein the block allocation metadata references one or more locations in the memory device corresponding to a zone; generating, by the host system, a reorder map based on the block allocation metadata; reading a plurality of data blocks associated with the zone; and reordering, by the host system, the plurality of data blocks based on the reorder map.

Abstract: A system includes a memory device, and a processing device, operatively coupled with the memory device, to perform operations including detecting a failure of a key-value store, identifying a non-filled zone of the memory device resulting from the failure, wherein the non-filled zone stores, in the key-value store, at least one of: an uncommitted key block or an uncommitted value block, and recovering the non-filled zone to obtain a recovered zone.

Abstract: A system includes a zoned memory device allocating a zone storing a block belonging to a key-value set, and a processing device, operatively coupled with the zoned memory device, to perform operations including obtaining zone status information associated with the zone, identifying that the zone is a non-filled zone in view of the zone status information, and recovering the non-filled zone to obtain a recovered zone.

Abstract: A system and method for reordering data blocks received from a zone of a memory device. An example method includes sending, by a host system to a memory sub-system comprising a memory device, a plurality of write commands; receiving, by the host system from the memory sub-system, block allocation metadata, wherein the block allocation metadata references one or more locations in the memory device corresponding to a zone; generating, by the host system, a reorder map based on the block allocation metadata; reading a plurality of data blocks associated with the zone; and reordering, by the host system, the plurality of data blocks based on the reorder map.

Abstract: A system includes a zoned memory device allocating a zone storing a block belonging to a key-value set, and a processing device, operatively coupled with the zoned memory device, to perform operations including obtaining zone status information associated with the zone, identifying that the zone is a non-filled zone in view of the zone status information, and recovering the non-filled zone to obtain a recovered zone.

Abstract: One or more input/output streams associated with one or more key-value databases can be received. Respective tags of the one or more input/output streams can be inspected. Based on identification data obtained from inspecting the respective tags, respective amounts of bandwidths to be provisioned to the one or more input/output streams can be determined in order to satisfy a threshold criterion pertaining to a predetermined quality-of-service (QoS) parameter associated with the one or more input/output streams. The one or more input/output streams with the respective amounts of provisioned bandwidths across the one or more key-value databases can be dynamically throttled to regulate processing time for input/output operations in the one or more input/output streams in accordance with the QoS parameter.

Abstract: Methods and systems for collision handling during an asynchronous replication are provided. A system includes a cache memory system comprising a number of cache memory pages. A collision detector detects when a host is attempting to overwrite a cache memory page that has not been completely replicated. A revision page tagger copies the cache memory page to a free page and tags the copied page as protected.

Abstract: Methods and systems for collision handling during an asynchronous replication are provided. A system includes a cache memory system comprising a number of cache memory pages. A collision detector detects when a host is attempting to overwrite a cache memory page that has not been completely replicated. A revision page tagger copies the cache memory page to a free page and tags the copied page as protected.

Abstract: Change-speed transmission providing multiple forward speeds and at least one reverse speed. An output shaft of the transmission carries a first speed pinion or gear that is rigid with a hollow shaft that carries, in turn, a gear or pinion of the reverse gear train disposed upstream of other forward speed gears or pinions. The reverse gear carries a dog that is separated from a dog carried by the closest forward speed gear by a dog and synchromesh unit. A layshaft mechanism is positioned parallel to the output shaft to increase the number of gear ratios provided by the transmission.