Abstract: The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal.

Abstract: The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal.

Abstract: A memory device including an array of memory cells arranged as a plurality of rows and columns. Write circuitry then controls a voltage level of the associated at least one bit line for each of the addressed memory cells to cause write data to be written into the addressed memory cells. In the presence of an asserted erase signal, a decoder circuitry's operation is modified such that it issues, independently of the clock signal, an asserted word line signal on the word line associated with each row in a predetermined erase region of the array. Further, the write circuitry's operation is modified so that it controls the voltage level of the associated at least one bit line for each memory cell in the predetermined erase region, in order to cause erase write data to be written into the memory cells of the predetermined erase region.