Abstract: Techniques for providing data protection in an integrated circuit are provided. An example method according to these techniques includes determining that an unauthorized update has been made to software or firmware associated with the integrated circuit, and corrupting an anti-replay counter (ARC) value, maintained in a one-time programmable memory of the integrated circuit and used by the integrated circuit to protect contents of a non-volatile memory, responsive to determining that the unauthorized update has been made to the software or the firmware.

Abstract: In certain aspects of the disclosure, a system includes an isolation device coupled between a first circuit in a first power domain and a second circuit in a second power domain. The system also includes a second power source coupled to a power distribution network, wherein the power distribution network is configured to distribute power from a first power source to the second power domain. The system further includes a failure detector having an input coupled to a node on the power distribution network located upstream of the second power source, and an output coupled to the isolation device, wherein the failure detector is configured to sense a voltage at the node, to detect a power loss of the first power source based on the sensed voltage, and to enable the isolation device in response to detection of the power loss.

Abstract: Various features relate to the providing Software-Resilient User Privacy within smartphones or other devices by storing and processing all pertinent values needed for user privacy—such as security keys and access attempt counters—in hardware, such as within a System-on-a-Chip (SoC) processor formed on an integrated circuit (IC). For example, an on-die ephemeral Volatile Memory (eVM) device may be employed for storing access attempt counters or other parameters used to control malicious attack countermeasures. In one example, the eVM employs static random-access memory (SRAM) formed on the die and exploits capacitive remanence to recover stored counter values even if power is disconnected, then reconnected. On-chip NVM may be used for permanent storage of other privacy values, such as a device-unique secret key that is generated locally on the device and not known to the chip vendor, the device Original Equipment Manufacturer (OEM)) or the owner/user of the device.

Abstract: In certain aspects of the disclosure, a system includes an isolation device coupled between a first circuit in a first power domain and a second circuit in a second power domain. The system also includes a second power source coupled to a power distribution network, wherein the power distribution network is configured to distribute power from a first power source to the second power domain. The system further includes a failure detector having an input coupled to a node on the power distribution network located upstream of the second power source, and an output coupled to the isolation device, wherein the failure detector is configured to sense a voltage at the node, to detect a power loss of the first power source based on the sensed voltage, and to enable the isolation device in response to detection of the power loss.

Abstract: In certain aspects of the disclosure, a chip includes an isolation device, wherein the isolation device is configured to allow a signal to pass from a first circuit in a first power domain to a second circuit in a second power domain via a signal line that crosses between the first and second power domains when the isolation device is disabled, and to clamp a portion of the signal line in the second power domain to a logic state when the isolation device is enabled. The chip also includes a failure detector configured to detect an imminent power failure of at least one of the first power domain or the second power domain, and to enable the isolation device in response to detection of the imminent power failure.

Abstract: Various embodiments include methods and devices for implementing protection of data by preventing non-authorized firmware modification on a computing device. Embodiments may include measuring, by a software program, an image of a firmware update producing a measurement of the image of the firmware update, modifying a version identifier of a prior installed firmware producing a version identifier of the firmware update, applying a root key generation algorithm to the measurement of the image of the firmware update, the version identifier of the firmware update, and an enroll identity credential, generating an enroll encryption root key as an output of the root key generation algorithm, applying a seed key encryption algorithm to the enroll encryption root key and an enroll encryption seed key, and generating a sealed encryption seed key as an output of the seed key encryption algorithm.

Abstract: In an aspect, an apparatus defines a group of registers that includes at least one of a plurality of registers in an integrated circuit. Each of the plurality of registers in the integrated circuit may be constrained to one of a plurality of fixed groups of registers. The apparatus applies a first set of access control rules to the group of registers, the first set of access control rules configured to override any of a second set of access control rules applied to the one or more fixed groups of registers.

Abstract: One feature pertains to a device that includes memory circuits having resource groups and access control circuitry. The access control circuitry establishes a tiered resource group access control scheme where security and access control properties of each resource group are managed by at least one of a hard governor execution environment or at least one soft governor execution environment. The access control circuitry also enforces access permissions of each resource group set by at least one of the hard governor execution environment or the at least one soft governor execution environment of each resource group.

Abstract: Techniques for providing data protection in an integrated circuit are provided. An example method according to these techniques includes determining that an unauthorized update has been made to software or firmware associated with the integrated circuit, and corrupting an anti-replay counter (ARC) value, maintained in a one-time programmable memory of the integrated circuit and used by the integrated circuit to protect contents of a non-volatile memory, responsive to determining that the unauthorized update has been made to the software or the firmware.

Abstract: Techniques for preventing tampering with programmable read-only memory of an integrated circuit are provided. A method according to these techniques includes performing a randomized read of data stored in the programmable read-only memory based on an input from an entropy source, writing the data to one or more registers of the integrated circuit, and initializing one or more components of the integrated circuit using the data stored in the one or more registers.

Abstract: In certain aspects of the disclosure, an apparatus includes first and second semaphore registers disposed in a first power domain. A common address bus is coupled to the first and second semaphore registers, and a semaphore lock is disposed in the first power domain and coupled to the first and second semaphore registers. The semaphore lock is controlled by the first and second semaphore registers, and controls whether a signal from a second power domain is permitted to propagate to the first power domain. The first and second semaphore registers may be associated with first and second register addresses, respectively, which are selected to provide a substantially maximized Hamming distance between them. The first and second semaphore registers may have a write order expectation enforced between them.

Abstract: Techniques for providing data protection in an integrated circuit are provided. A method according to these techniques includes maintaining an anti-replay counter value in a volatile memory of the integrated circuit, the anti-replay counter value being associated with data stored in an off-chip, non-volatile memory in which the integrated circuit is configured to store the data, monitoring an external power source, and writing the anti-replay counter value to a programmable read-only memory of the integrated circuit responsive to a loss of power to the integrated circuit from the external power source.

Abstract: Techniques for maintaining an anti-replay counter (ARC) for providing data protection in an integrated circuit are provided. A method according to these techniques includes determining a static baseline value based on an ARC value stored in a programmable read-only memory of the integrated circuit, determining the ARC value based on the static baseline value and a transient component, and storing the ARC value in a volatile memory of the integrated circuit.

Abstract: In certain aspects of the disclosure, a chip includes an isolation device, wherein the isolation device is configured to allow a signal to pass from a first circuit in a first power domain to a second circuit in a second power domain via a signal line that crosses between the first and second power domains when the isolation device is disabled, and to clamp a portion of the signal line in the second power domain to a logic state when the isolation device is enabled. The chip also includes a failure detector configured to detect an imminent power failure of at least one of the first power domain or the second power domain, and to enable the isolation device in response to detection of the imminent power failure.

Abstract: In certain aspects of the disclosure, an apparatus includes first and second semaphore registers disposed in a first power domain. A common address bus is coupled to the first and second semaphore registers, and a semaphore lock is disposed in the first power domain and coupled to the first and second semaphore registers. The semaphore lock is controlled by the first and second semaphore registers, and controls whether a signal from a second power domain is permitted to propagate to the first power domain. The first and second semaphore registers may be associated with first and second register addresses, respectively, which are selected to provide a substantially maximized Hamming distance between them. The first and second semaphore registers may have a write order expectation enforced between them.

Abstract: Techniques for preventing tampering with programmable read-only memory of an integrated circuit are provided. A method according to these techniques includes performing a randomized read of data stored in the programmable read-only memory based on an input from an entropy source, writing the data to one or more registers of the integrated circuit, and initializing one or more components of the integrated circuit using the data stored in the one or more registers.

Abstract: Various features relate to the providing Software-Resilient User Privacy within smartphones or other devices by storing and processing all pertinent values needed for user privacy—such as security keys and access attempt counters—in hardware, such as within a System-on-a-Chip (SoC) processor formed on an integrated circuit (IC). For example, an on-die ephemeral Volatile Memory (eVM) device may be employed for storing access attempt counters or other parameters used to control malicious attack countermeasures. In one example, the eVM employs static random-access memory (SRAM) formed on the die and exploits capacitive remanence to recover stored counter values even if power is disconnected, then reconnected. On-chip NVM may be used for permanent storage of other privacy values, such as a device-unique secret key that is generated locally on the device and not known to the chip vendor, the device Original Equipment Manufacturer (OEM)) or the owner/user of the device.

Abstract: Techniques for providing data protection in an integrated circuit are provided. A method according to these techniques includes maintaining an anti-replay counter value in a volatile memory of the integrated circuit, the anti-replay counter value being associated with data stored in an off-chip, non-volatile memory in which the integrated circuit is configured to store the data, monitoring an external power source, and writing the anti-replay counter value to a programmable read-only memory of the integrated circuit responsive to a loss of power to the integrated circuit from the external power source.

Abstract: Techniques for maintaining an anti-replay counter (ARC) for providing data protection in an integrated circuit are provided. A method according to these techniques includes determining a static baseline value based on an ARC value stored in a programmable read-only memory of the integrated circuit, determining the ARC value based on the static baseline value and a transient component, and storing the ARC value in a volatile memory of the integrated circuit.

Abstract: Process for the preparation of a compound of general formula (I): in which X represents a halogen atom, by reaction of para-trifluoromethylaniline of formula (II): with a dihalogen X2, the two compounds being introduced simultaneously into a polar aprotic solvent in a dihalogen/compound (II) molar ratio ranging from 1.9 to 2.5 and at a temperature ranging from 100 to 300° C.