Abstract: A system for the management of the physical memory of a processor which utilizes a base register which is loaded, for each virtual address of the memory, by a base address of a discriptive register corresponding to a task to be performed by the processor. This system utilizes a descriptive register table, an adder receiving the binary value of the base address of the first descriptive register, and the binary value of the index corresponding to the first register. The outputs of the adder address one of the inputs of the descriptive register table, thus selecting a segment descriptive register corresponding to the task to be performed. Each of the descriptive registers of the table contains control bits sent to the processor which makes it possible for the processor to check whether, for the segment to which the processor must have access, the processor must operate in the local or overall mode and whether the processor must process an input-output operation or an access to the memory.

Abstract: The invention relates to an access system to several processors having common resources by means of a common bus.For each processor this system comprises an arbitration means for access request conflicts. The arbitration means comprises access request processing means connected to the bus and to the processor and an access priority resolution circuit connected to the bus, to the access request processing means and to the processor. The resolution circuit is able to allocate mixed, cyclic or mixed fixed and cyclic priorities to the access requests.Application to the management of access requests for processors or microprocessors having common resources, such as memories.