Abstract: The invention concerns a device for processing signals in the form of successive packets sent in successive time slots of the type comprising a processing system including at least one processing member with secondary effects (81, 82) likely to generate disturbances affecting adjacent packets. Two processor members (81, 82) with secondary effects are disposed in separate channels (90, 91) and switching means (83, 84) cyclically connect the separate channels each during one time slot and disconnect them between times so that a channel connected to process a packet cannot be disturbed by adjacent packets each processed by another channel.

Abstract: In a method of detecting false locks between a reference signal and an input signal to be demodulated to produce a coherent demodulated signal comprising a number of phase states, the level of the input signal at a predetermined moment in the bit period of the input signal after demodulation and before regeneration is compared with the level of the input signal after regeneration, bit by bit. The reference signal is optionally corrected so as to lock its reference and phase to the input signal.