Abstract: A circuit for performing neural network computations for a neural network is described. The circuit includes plurality of neural network layers each including a crossbar arrays. The plurality of crossbar arrays are formed in a common substrate in a stacked configuration. Each crossbar array includes a set of crosspoint devices. A respective electrical property of each of the crosspoint devices is adjustable to represent a weight value that is stored for each respective crosspoint device. A processing unit is configured to adjust the respective electrical properties of each of the crosspoint devices by pre-loading each of the crosspoint devices with a tuning signal. A value of the turning signal for each crosspoint device is a function of the weight value represented by each respective crosspoint device.

Abstract: A computing unit for accelerating a neural network is disclosed. The computing unit include an input unit that includes a digital-to-analog conversion unit and an analog-to-digital conversion unit that is configured to receive an analog signal from the output of a last interconnected analog crossbar circuit of a plurality of analog crossbar circuits and convert the second analog signal into a digital output vector, and a plurality of interconnected analog crossbar circuits that include the first interconnected analog crossbar circuit and the last interconnected crossbar circuits, wherein a second interconnected analog crossbar circuit of the plurality of interconnected analog crossbar circuits is configured to receive a third analog signal from another interconnected analog crossbar circuit of the plurality of interconnected crossbar circuits and perform one or more operations on the third analog signal based on the matrix weights stored by the crosspoints of the second interconnected analog crossbar.

Abstract: A computing unit for accelerating a neural network is disclosed. The computing unit may include an input unit that includes a digital-to-analog conversion unit and an analog-to-digital conversion unit that is configured to receive an analog signal from the output of a last interconnected analog crossbar circuit of a plurality of analog crossbar circuits and convert the second analog signal into a digital output vector, and a plurality of interconnected analog crossbar circuits that include the first interconnected analog crossbar circuit and the last interconnected crossbar circuits, wherein a second interconnected analog crossbar circuit of the plurality of interconnected analog crossbar circuits is configured to receive a third analog signal from another interconnected analog crossbar circuit of the plurality of interconnected crossbar circuits and perform one or more operations on the third analog signal based on the matrix weights stored by the crosspoints of the second interconnected analog crossbar.

Abstract: A circuit for performing neural network computations for a neural network is described. The circuit includes plurality of neural network layers each including a crossbar arrays. The plurality of crossbar arrays are formed in a common substrate in a stacked configuration. Each crossbar array includes a set of crosspoint devices. A respective electrical property of each of the crosspoint devices is adjustable to represent a weight value that is stored for each respective crosspoint device. A processing unit is configured to adjust the respective electrical properties of each of the crosspoint devices by pre-loading each of the crosspoint devices with a tuning signal. A value of the turning signal for each crosspoint device is a function of the weight value represented by each respective crosspoint device.

Abstract: A circuit for performing neural network computations for a neural network is described. The circuit includes plurality of neural network layers each including a crossbar arrays. The plurality of crossbar arrays are formed in a common substrate in a stacked configuration. Each crossbar array includes a set of crosspoint devices. A respective electrical property of each of the crosspoint devices is adjustable to represent a weight value that is stored for each respective crosspoint device. A processing unit is configured to adjust the respective electrical properties of each of the crosspoint devices by pre-loading each of the crosspoint devices with a tuning signal. A value of the turning signal for each crosspoint device is a function of the weight value represented by each respective crosspoint device.

Abstract: Embedded air gap transmission lines and methods of fabrication are provided. An apparatus having an air gap transmission line can include a first conductive plane, a core dielectric layer having a bottom surface in contact with the first conductive plane, a conductor having a bottom surface in contact with a top surface of the core dielectric layer, and a second conductive plane positioned over, and spaced apart from, a top surface of the conductor such that a gap separates the conductor from the second conductive plane. The top surface of the conductor is separated from the bottom surface of the second conductive plane by a first distance measured along an axis normal to the first conductive plane, and the bottom surface of the conductor is separated from the first conductive plane by a second distance greater than the first distance measured along the axis.

Abstract: A circuit for performing neural network computations for a neural network is described. The circuit includes plurality of neural network layers each including a crossbar arrays. The plurality of crossbar arrays are formed in a common substrate in a stacked configuration. Each crossbar array includes a set of crosspoint devices. A respective electrical property of each of the crosspoint devices is adjustable to represent a weight value that is stored for each respective crosspoint device. A processing unit is configured to adjust the respective electrical properties of each of the crosspoint devices by pre-loading each of the crosspoint devices with a tuning signal. A value of the turning signal for each crosspoint device is a function of the weight value represented by each respective crosspoint device.

Abstract: A computing unit for accelerating a neural network is disclosed. The computing unit may include an input unit that includes a digital-to-analog conversion unit and an analog-to-digital conversion unit that is configured to receive an analog signal from the output of a last interconnected analog crossbar circuit of a plurality of analog crossbar circuits and convert the second analog signal into a digital output vector, and a plurality of interconnected analog crossbar circuits that include the first interconnected analog crossbar circuit and the last interconnected crossbar circuits, wherein a second interconnected analog crossbar circuit of the plurality of interconnected analog crossbar circuits is configured to receive a third analog signal from another interconnected analog crossbar circuit of the plurality of interconnected crossbar circuits and perform one or more operations on the third analog signal based on the matrix weights stored by the crosspoints of the second interconnected analog crossbar.

Abstract: A circuit for performing neural network computations for a neural network is described. The circuit includes plurality of neural network layers each including a crossbar arrays. The plurality of crossbar arrays are formed in a common substrate in a stacked configuration. Each crossbar array includes a set of crosspoint devices. A respective electrical property of each of the crosspoint devices is adjustable to represent a weight value that is stored for each respective crosspoint device. A processing unit is configured to adjust the respective electrical properties of each of the crosspoint devices by pre-loading each of the crosspoint devices with a tuning signal. A value of the turning signal for each crosspoint device is a function of the weight value represented by each respective crosspoint device.

Abstract: At least one aspect is directed to a IC socket with impedance-controlled signal lines. The IC socket includes a first plurality of signal contacts configured to make electrical connections to leads of an integrated circuit, a second plurality of signal contacts configured to make electrical connections to pads of a printed circuit board, a substrate disposed between the first and second pluralities of signal contacts, and a plurality of signal lines passing through the substrate. The substrate comprises a plurality of layers, the layers alternating between dielectric layers and at least one conductor layer. Each signal line electrically connects a first signal contact of the first plurality of signal contacts with a second signal contact of the second plurality of signal contacts. Each conductor layer defines a gap around each signal line. The proximity of each signal line to each conductor layer creates a capacitance between the two.

Abstract: Circuits, methods, and apparatus that are capable of processing graphics information and wirelessly transmitting processed graphics information to a monitor. In order to achieve a high bandwidth, one embodiment of the present invention provides a graphics processor chip that includes multiple RF transmitters such that processed graphics information can be transmitted using the cumulative bandwidth of multiple wireless channels. These transmitters can use one or more RF standards or proprietary signaling schemes.

Abstract: Circuits, methods, and apparatus that are capable of processing graphics information and wirelessly transmitting processed graphics information to a monitor. In order to achieve a high bandwidth, one embodiment of the present invention provides a graphics processor chip that includes multiple RF transmitters such that processed graphics information can be transmitted using the cumulative bandwidth of multiple wireless channels. These transmitters can use one or more RF standards or proprietary signaling schemes.

Abstract: Circuits, methods, and apparatus that are capable of processing graphics information and wirelessly transmitting processed graphics information to a monitor. In order to achieve a high bandwidth, one embodiment of the present invention provides a graphics processor chip that includes multiple RF transmitters such that processed graphics information can be transmitted using the cumulative bandwidth of multiple wireless channels. These transmitters can use one or more RF standards or proprietary signaling schemes.