Abstract: A field effect transistor having a T-gate (10), the gate comprising a neck portion (16) and a T-bar portion (18) overhanging the neck portion, wherein the neck portion (16) comprises a plurality of spaced pillars (20). By forming the neck portion from a plurality of spaced pillars the area of contact between the gate and the channel, or “effective gate width”, is reduced whilst the T-bar portion (18) ensures electrical continuity through the gate by bridging the pillars (20). This reduces the input gate capacitance, thereby giving an FET having an increased device performance.

Abstract: A HEMT has a substrate (2), buffer layer (4), channel layer (8), spacer layer (10), delta doped layer (12), Schottky barrier layer (14) and cap layer (18) and metal layer (20), the latter forming a Schottky barrier with the underlying semiconductor. The channel may be of GaInAs and the barrier (4), spacer (10) and Schottky barrier layers (14) may be of AlInAs. An additional thin layer for example of GaAs is added between the Schottky barrier layer (14) and metallic layer (18) to enhance the Schottky barrier height without creating excessive defects.