Abstract: A photosensitive sensor is capable of operating in a global shutter mode and in a rolling shutter mode. The sensor includes at least one pixel with a photosensitive region configured to photogenerate charges. A first transfer gate is configured to transfer photogenerated charges from the photosensitive region to a transfer node. A source-follower transistor is configured to transmit a reading signal to a read node, in the global shutter mode, in a manner controlled by a potential of the photogenerated charges on the transfer node. A second transfer gate is configured to transfer the photogenerated charges from the photosensitive region to the read node in the rolling shutter mode.

Abstract: The present disclosure relates to an image sensor that includes first and second pixels. One or more transistors of the first pixel share an active region with one or more transistors of the second pixel.

Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.

Abstract: In an embodiment a method for measuring ambient light includes successively synchronizing optical signal acquisition phases with extinction phases of a disruptive light source, wherein the disruptive light source periodically provides illumination phases and the extinction phases, accumulating, in each acquisition phase, photo-generated charges by at least one photosensitive pixel comprising a pinned photodiode, wherein an area of the pinned photodiode is less than or equal to 1/10 of an area of the at least one photosensitive pixel, transferring, for each pixel, the accumulated photo-generated charges to a sensing node, converting, for each pixel, the transferred charges to a voltage at a voltage node and converting, for each pixel, the transferred charges to a digital number.

Abstract: An image sensor includes pixels each including: a first transistor and a first switch that are connected in series between a first node configured to receive a first potential and an internal node of the pixel, a gate of the first transistor being coupled with a floating diffusion node of the pixel; a capacitive element, a first terminal of which is connected to the floating diffusion node of the pixel; and several assemblies each including a capacitance connected in series with a second switch coupling the capacitance to the internal node. The sensor also includes a control circuit configured to control, each time a voltage is stored in one of the assemblies of a pixel, an increase of a determined value of a difference in potential between the floating diffusion node and the internal node of the pixel.

Abstract: The present description concerns a sensor and method. Each pixel of the sensor comprises assemblies each including a memory area and a transfer device coupling the memory area to a photoconversion area, and a device for resetting the memory areas. The sensor includes a first circuit controlling the transfer devices and a second circuit controlling the reset devices. During each integration phase, the second circuit orders the end of a phase of reset of the memory areas of first pixels at the beginning of the integration phase and the end of a phase of reset of the memory areas of second pixels at a time subsequent to the beginning of the integration phase.

Abstract: A sensor includes pixels each including: a first transistor and a first switch in series between a first node and an internal node of the pixel, a gate of the first transistor being coupled to a second node; a capacitive element, a first terminal of which is connected to the second node; and a plurality of assemblies each including a capacitance in series with a second switch coupled to the internal node. The sensor includes a circuit configured to control, each time a voltage is stored in one of the assemblies, the interruption of a current between the first node and the internal node: by switching a first potential applied to a second terminal of the capacitive element; or by opening the first switch.

Abstract: In one embodiment, an integrated image sensor includes an array of pixels in which each pixel includes a photosensitive area configured to integrate a luminous signal by generating electron-hole pairs so as to form a first signal representative of the number of electrons in the generated electron-hole pairs and a second signal representative of the number of holes in the generated electron-hole pairs. A first circuit portion is configured to store the first signal sheltered from light. A second circuit portion is configured to store the second signal sheltered from light. A third circuit portion is configured to read the first signal and the second signal and able to perform combination operations between the first signal and the second signal so as to generate a combined signal representative of an image, where the integrated image sensor is tailored to operate in a global shutter control mode.

Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.

Abstract: A pixel of an imager device includes a photosensitive area configured to integrate a light signal. A first capacitive storage node is configured to receive a signal representative of the number of charges generated by the photosensitive area. A second capacitive storage node is configured to receive a reference signal. A first transfer transistor is coupled between the first capacitive storage node and the photosensitive area. A second transfer transistor is coupled between the second capacitive storage node and a terminal which supplied the reference signal. The first and second two transfer transistors have a common conduction electrode and a common substrate, wherein the common substrate is coupled to the first capacitive storage node.

Abstract: In one embodiment, an integrated image sensor includes an array of pixels in which each pixel includes a photosensitive area configured to integrate a luminous signal by generating electron-hole pairs so as to form a first signal representative of the number of electrons in the generated electron-hole pairs and a second signal representative of the number of holes in the generated electron-hole pairs. A first circuit portion is configured to store the first signal sheltered from light. A second circuit portion is configured to store the second signal sheltered from light. A third circuit portion is configured to read the first signal and the second signal and able to perform combination operations between the first signal and the second signal so as to generate a combined signal representative of an image, where the integrated image sensor is tailored to operate in a global shutter control mode.

Abstract: An image sensor includes a plurality of pixels each including a first photodiode linked to a capacitive readout node by a first transistor, and a second photodiode linked to a first capacitive storage node by a second transistor, the first capacitive node being linked to the readout node by a third transistor, and the readout node being linked to a node for applying a reset potential by a fourth transistor.

Abstract: An image sensor includes a plurality of pixels each including a first photodiode linked to a capacitive readout node by a first transistor, and a second photodiode linked to a first capacitive storage node by a second transistor, the first capacitive node being linked to the readout node by a third transistor, and the readout node being linked to a node for applying a reset potential by a fourth transistor.

Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active area that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that forms the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.

Abstract: Methodology enabling a reduction of edge and strap cell size, and the resulting device are disclosed. Embodiments include: providing first and second NW regions on a substrate; providing first and second RX regions on the first and second NW regions, respectively; providing a contact on the substrate connecting the first and second RX regions; and providing a dummy PC on the substrate connecting the first and second RX regions. Other embodiments include: determining an RX region of an IC design; determining a PPLUS mask region extending along a horizontal direction and being on an entire upper surface of the RX region; determining a NW region extending along a vertical direction and separated from the RX region; and comparing an area of an overlap of the NW region and PPLUS mask region to a threshold value.

Abstract: Methodology enabling a reduction of edge and strap cell size, and the resulting device are disclosed. Embodiments include: providing first and second NW regions on a substrate; providing first and second RX regions on the first and second NW regions, respectively; providing a contact on the substrate connecting the first and second RX regions; and providing a dummy PC on the substrate connecting the first and second RX regions. Other embodiments include: determining an RX region of an IC design; determining a PPLUS mask region extending along a horizontal direction and being on an entire upper surface of the RX region; determining a NW region extending along a vertical direction and separated from the RX region; and comparing an area of an overlap of the NW region and PPLUS mask region to a threshold value.

Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active are that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that form the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.

Abstract: A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.

Abstract: A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.

Abstract: A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.