Abstract: The present disclosure generally relates to a swine feed or swine feed product including insect oil, for example about 0.1 wt % to about 10.0 wt %. In general, the insect oil comprises lauric acid, for example, at least 35% lauric acid. Also provided are methods for feeding a pig, in particular a sow or piglet, said swine feed.

Abstract: A system for measuring a market performance metric of an animal comprising: a sensor unit that detects an emitted spectrum from the animal wherein the sensor unit filters the received emitted spectra to a set of spectral values; and a memory unit that comprises a set of predetermined chemometric data correlated to at least the market performance metric, wherein the memory unit is correlated to the set of spectral values.

Abstract: A method is provided for regulating an actual value of a variable, which characterizes a position of an actuator, to a setpoint value using a regulator, which method makes it possible to optimize regulation in terms of bandwidth, stability, accuracy, and sturdiness. A predefined time characteristic of the setpoint value is transformed into a desired time characteristic of the actual value. A first transfer function is formed in the frequency domain and is approximated using one or more factors, in particular delay elements, to transform the predefined time characteristic of the setpoint value into the desired time characteristic of the actual value. A nonintegral exponent is selected for at least one of the factors.

Abstract: A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.

Abstract: A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.

Abstract: The frequency synthesizer includes a phase-locked loop (PLL). The PLL includes an oscillator controlled to deliver an output signal at a predefined output frequency, a variable frequency divider to convert the output signal into a divided-frequency signal, a phase comparator to produce a signal measuring a phase difference between the divided-frequency signal and a reference signal at a reference frequency, and a loop filter to control the oscillator on the basis of the measurement signal. To increase the speed of convergence of the synthesizer if the set point is changed, the loop filter of the PLL is a fractional, i.e. non-integer, order low-pass filter.